Feng Gao

US Patent:

6486081, Nov 26, 2002

Filed:

Nov 24, 1999

Appl. No.:

09/449203

Inventors:

Tetsuya Ishikawa - Santa Clara CA
Padmanabhan Krishnaraj - Mountain View CA
Feng Gao - Mountain View CA
Alan W. Collins - San Francisco CA
Lily Pang - Fremont CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 2131

US Classification:

438788, 438787, 438789, 438792

Abstract:

The present invention provides an apparatus for depositing a film on a substrate comprising a processing chamber, a substrate support member disposed within the chamber, a first gas inlet, a second gas inlet, a plasma generator and a gas exhaust. The first gas inlet provides a first gas at a first distance from an interior surface of the chamber, and the second gas inlet provides a second gas at a second distance that is closer than the first distance from the interior surface of the chamber. Thus, the second gas creates a higher partial pressure adjacent the interior surface of the chamber to significantly reduce deposition from the first gas onto the interior surface. The present invention also provides a method for depositing a FSG film on a substrate comprising: introducing first gas through a first gas inlet at a first distance from an interior surface of the chamber, and introducing a second gas through a second gas inlet at a second distance from the interior surface of the chamber, wherein the second gas creates a higher partial pressure adjacent the interior surface of the chamber to prevent deposition from the first gas on the interior surface. Alternatively, the first gas is introduced at a different angle from the second gas with respect to a substrate surface.

US Patent:

6541263, Apr 1, 2003

Filed:

Feb 21, 2001

Appl. No.:

09/788353

Inventors:

Feng Gao - Stamford CT

Assignee:

Euro-Celtique, S.A. Luxembourg

International Classification:

G01N 3392

US Classification:

436 71, 436101, 436173, 436139

Abstract:

The present invention is directed to a method of detecting a corticosteroid in a sample by adding an internal standard to a sample suspected of containing a corticosteroid; removing interfering compounds from the sample; placing the sample on an HPLC column equilibrated with a NH OAc:MeOH solution and collecting an eluent; and analyzing the eluent of the HPLC column with a MS, wherein if contained in the sample, the corticosteroid forms an adduct that is detected by the MS.

US Patent:

6660662, Dec 9, 2003

Filed:

Jan 26, 2001

Appl. No.:

09/771203

Inventors:

Tetsuya Ishikawa - Santa Clara CA
Alexandros T. Demos - San Ramon CA
Feng Gao - Mountain View CA
Kaveh F. Niazi - Santa Clara CA
Michio Aruga - Inba-Gun, JP

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 2144

US Classification:

438787, 438680, 438681, 438788

Abstract:

A method is provided for depositing a thin film on a substrate in a process chamber with reduced incidence of plasma charge damage. A process gas containing a precursor gases suitable for forming a plasma is flowed into a process chamber, and a plasma is generated from the process gas to deposit the thin film on the substrate. The precursor gases are flowed into the process chamber such that the thin film is deposited at the center of the substrate more rapidly than at an edge of the substrate.

US Patent:

6740641, May 25, 2004

Filed:

Jul 22, 2002

Appl. No.:

10/199526

Inventors:

Feng Gao - Stamford CT
Jahanara Miotto - Carmel NY

Assignee:

Euro-Celtique, S.A.

International Classification:

A01N 4304

US Classification:

514 27, 514281, 514282, 546 44, 546 45, 546 46, 424 7829

Abstract:

Glucoside and glucuronide derivatives of hydromorphone, dihydromorphine, and dihydroisomorphine and pharmaceutically acceptable salts thereof; pharmaceutical compositions comprising a glucoside or glucuronide derivative of hydromorphone, dihydromorphine, or dihydroisomorphine or a pharmaceutically acceptable salt thereof; and methods for treating or preventing pain in a patient comprising administering to a patient in need thereof a glucoside or glucuronide derivative of hydromorphone, dihydromorphine, or dihydroisomorphine or a pharmaceutically acceptable salt thereof are disclosed.

US Patent:

6814814, Nov 9, 2004

Filed:

Mar 29, 2002

Appl. No.:

10/109736

Inventors:

Alan W. Collins - San Francisco CA
Feng Gao - Fremont CA
Tetsuya Ishikawa - Santa Clara CA
Padmanaban Krishnaraj - San Francisco CA
Yaxin Wang - Fremont CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

B08B 312

US Classification:

134 1, 134 11, 134 221, 134 22, 134 30, 134 56 R, 134 951, 134166 R, 216 37, 216 67, 216 71, 438714, 438905, 438906

Abstract:

In a method of cleaning process residues formed on surfaces in a substrate processing chamber, a sacrificial substrate comprising a sacrificial material is placed in the chamber, a sputtering gas is introduced into the chamber, and the sputtering gas is energized to sputter the sacrificial material from the substrate. The sputtered sacrificial material reacts with residues on the chamber surfaces to clean them. In one version, the sacrificial substrate comprises a silicon-containing material that when sputtered deposits silicon on the chamber walls that reacts with and cleans fluorine-containing species that are left behind by a chamber cleaning process.

US Patent:

6927993, Aug 9, 2005

Filed:

Aug 14, 2003

Appl. No.:

10/642079

Inventors:

Bomy Chen - Cupertino CA, US
Kai Man Yue - Yuen Long, HK
Dana Lee - Santa Clara CA, US
Feng Gao - Sunnyvale CA, US

Assignee:

Silicon Storage Technology, Inc. - Sunnyvale CA

International Classification:

G11C017/00

US Classification:

365104, 365 94

Abstract:

A array of multi-bit Read Only Memory (ROM) cells is in a semiconductor substrate of a first conductivity type with a first concentration. Each ROM cell has a first and second regions of a second conductivity type spaced apart from one another in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. Each ROM cell has one of a plurality of N possible states, where N is greater than 2. The state of each ROM cell is determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost. The array of ROM cells are arranged in a plurality of rows and columns, with ROM cells in the same row having their gates connected together.

US Patent:

6992909, Jan 31, 2006

Filed:

Jun 20, 2005

Appl. No.:

11/157318

Inventors:

Bomy Chen - Cupertino CA, US
Kai Man Yue - Yuen Long N.T., HK
Dana Lee - Santa Clara CA, US
Feng Gao - Sunnyvale CA, US

Assignee:

Silicon Storage Techtology, Inc. - Sunnyvale CA

International Classification:

G11C 17/00

US Classification:

365 94, 365104, 438527

Abstract:

A array of multi-bit Read Only Memory (ROM) cells is in a semiconductor substrate of a first conductivity type with a first concentration. Each ROM cell has a first and second regions of a second conductivity type spaced apart from one another in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. Each ROM cell has one of a plurality of N possible states, where N is greater than 2. The state of each ROM cell is determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost. The array of ROM cells are arranged in a plurality of rows and columns, with ROM cells in the same row having their gates connected together.

US Patent:

7036453, May 2, 2006

Filed:

Sep 8, 2003

Appl. No.:

10/658350

Inventors:

Tetsuya Ishikawa - Santa Clara CA, US
Alexandros T. Demos - San Ramon CA, US
Feng Gao - Mountain View CA, US
Kaveh F. Niazi - Santa Clara CA, US
Michio Aruga - Inba-Gun, JP

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

C23C 16/00

US Classification:

118723R, 118715, 438787, 438788

Abstract:

A method is provided for depositing a thin film on a substrate in a process chamber with reduced incidence of plasma charge damage. A process gas containing a precursor gases suitable for forming a plasma is flowed into a process chamber, and a plasma is generated from the process gas to deposit the thin film on the substrate. The precursor gases are flowed into the process chamber such that the thin film is deposited at the center of the substrate more rapidly than at an edge of the substrate.

Address:

3251 Pomerado Dr, San Jose, CA 95135

VIN:

1D4GP25B47B153434

Make:

DODGE

Model:

CARAVAN

Year:

2007