Feng Juan Gao

US Patent:

6814814, Nov 9, 2004

Filed:

Mar 29, 2002

Appl. No.:

10/109736

Inventors:

Alan W. Collins - San Francisco CA
Feng Gao - Fremont CA
Tetsuya Ishikawa - Santa Clara CA
Padmanaban Krishnaraj - San Francisco CA
Yaxin Wang - Fremont CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

B08B 312

US Classification:

134 1, 134 11, 134 221, 134 22, 134 30, 134 56 R, 134 951, 134166 R, 216 37, 216 67, 216 71, 438714, 438905, 438906

Abstract:

In a method of cleaning process residues formed on surfaces in a substrate processing chamber, a sacrificial substrate comprising a sacrificial material is placed in the chamber, a sputtering gas is introduced into the chamber, and the sputtering gas is energized to sputter the sacrificial material from the substrate. The sputtered sacrificial material reacts with residues on the chamber surfaces to clean them. In one version, the sacrificial substrate comprises a silicon-containing material that when sputtered deposits silicon on the chamber walls that reacts with and cleans fluorine-containing species that are left behind by a chamber cleaning process.

US Patent:

7247907, Jul 24, 2007

Filed:

May 20, 2005

Appl. No.:

11/134557

Inventors:

Feng Gao - Sunnyvale CA, US
Ya-Fen Lin - Santa Clara CA, US
John W. Cooksey - Brentwood CA, US
Changyuan Chen - Sunnyvale CA, US
Yuniarto Widjaja - San Jose CA, US
Dana Lee - Santa Clara CA, US

Assignee:

Silicon Storage Technology, Inc. - Sunnyvale CA

International Classification:

H01L 29/788

US Classification:

257315, 257316, 257321, 257324, 257326, 438201, 438257, 438258

Abstract:

A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type and a second region of the second conductivity type in the substrate, spaced apart from the first region, thereby defining a channel region therebetween. A plurality of floating gates are spaced apart from one another and each is insulated from the channel region. A plurality of control gates are spaced apart from one another, with each control gate insulated from the channel region. Each of the control gate is between a pair of floating gates and is capacitively coupled to the pair of floating gates. A plurality of select gates are spaced apart from one another, with each select gate insulated from the channel region. Each select gate is between a pair of floating gates.

US Patent:

7351357, Apr 1, 2008

Filed:

Feb 26, 2003

Appl. No.:

10/374875

Inventors:

Feng Gao - Wilmington DE, US

Assignee:

E.I. du Pont de Nemours and Company - Wilmington DE

International Classification:

H01B 1/04
H01B 1/12
B05D 5/12

US Classification:

252500, 252510, 427 961, 427122

Abstract:

Additives to organic conducting polymers are described which enhance adhesion and resolution of printed films while retaining adequate electrical conductivity. The conductive polymer films are useful in printing conductive portions of thin film transistors such as sources and drains. Additives include surfactants, second macromolecules, plasticizers, and excess sulfonic acids.

US Patent:

7544569, Jun 9, 2009

Filed:

Sep 5, 2006

Appl. No.:

11/516431

Inventors:

Feng Gao - Sunnyvale CA, US
Ya-Fen Lin - Santa Clara CA, US
John W. Cooksey - Brentwood CA, US
Changyuan Chen - Sunnyvale CA, US
Yuniarto Widjaja - San Jose CA, US
Dana Lee - Santa Clara CA, US

Assignee:

Silicon Storage Technology, Inc. - Sunnyvale CA

International Classification:

H01L 21/336

US Classification:

438266, 438257, 438258, 438261, 438262, 438264, 438287, 438288, 438622, 438672, 257E21679, 257E21681

Abstract:

A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type and a second region of the second conductivity type in the substrate, spaced apart from the first region, thereby defining a channel region therebetween. A plurality of floating gates are spaced apart from one another and each is insulated from the channel region. A plurality of control gates are spaced apart from one another, with each control gate insulated from the channel region. Each of the control gate is between a pair of floating gates and is capacitively coupled to the pair of floating gates. A plurality of select gates are spaced apart from one another, with each select gate insulated from the channel region. Each select gate is between a pair of floating gates.

US Patent:

20050116202, Jun 2, 2005

Filed:

Feb 26, 2003

Appl. No.:

10/501603

Inventors:

Feng Gao - Wilmington DE, US

International Classification:

H01C001/00

US Classification:

252500000

Abstract:

Additives to organic conducting polymers are described which enhance adhesion and resolution of printed films while retaining adequate electrical conductivity. The conductive polymer films are useful in printing conductive portions of thin film transistors such as sources and drains. Additives include surfactants, second macromolecules, plasticizers, and excess sulfonic acids.

US Patent:

20060017084, Jan 26, 2006

Filed:

Jul 22, 2004

Appl. No.:

10/897045

Inventors:

Feng Gao - Sunnyvale CA, US
Changyuan Chen - Sunnyvale CA, US
Vishal Sarin - Cupertino CA, US
William Saiki - Mountain View CA, US
Hieu Tran - San Jose CA, US
Dana Lee - Santa Clara CA, US

International Classification:

H01L 29/76

US Classification:

257296000

Abstract:

An integrated MIS capacitor has two substantially identical MIS capacitors. A first capacitor comprises a first region of a first conductivity type adjacent to a channel region of the first conductivity type in a semiconductor substrate. The semiconductor substrate has a second conductivity type. A gate electrode is insulated and spaced apart from the channel region of the first capacitor. The second capacitor is substantially identical to the first capacitor and is formed in the same semiconductor substrate. The gate electrode of the first capacitor is electrically connected to the first region of the second capacitor and the gate electrode of the second capacitor is electrically connected to the first region of the first capacitor. In this manner, the capacitors are connected in an anti-parallel configuration. A capacitor which has high capacitance densities, low process complexity, ambipolar operation, low voltage and temperature coefficient, low external parasitic resistance and capacitance and good matching characteristics for use in analog designs that can be integrated with existing semiconductor processes results.

US Patent:

20090096507, Apr 16, 2009

Filed:

Nov 13, 2008

Appl. No.:

12/270604

Inventors:

Feng Gao - Sunnyvale CA, US
Changyuan Chen - Sunnyvale CA, US
Vishal Sarin - Cupertino CA, US
William John Saiki - Mountain View CA, US
Hieu Van Tran - San Jose CA, US
Dana Lee - Santa Clara CA, US

Assignee:

Silicon Storage Technology, Inc. - Sunnyvale CA

International Classification:

H03K 3/01

US Classification:

327534

Abstract:

An integrated MIS capacitor has two substantially identical MIS capacitors. A first capacitor comprises a first region of a first conductivity type adjacent to a channel region of the first conductivity type in a semiconductor substrate. The semiconductor substrate has a second conductivity type. A gate electrode is insulated and spaced apart from the channel region of the first capacitor. The second capacitor is substantially identical to the first capacitor and is formed in the same semiconductor substrate. The gate electrode of the first capacitor is electrically connected to the first region of the second capacitor and the gate electrode of the second capacitor is electrically connected to the first region of the first capacitor. In this manner, the capacitors are connected in an anti-parallel configuration. A capacitor which has high capacitance densities, low process complexity, ambipolar operation, low voltage and temperature coefficient, low external parasitic resistance and capacitance and good matching characteristics for use in analog designs that can be integrated with existing semiconductor processes results.

US Patent:

20090323098, Dec 31, 2009

Filed:

Jun 25, 2008

Appl. No.:

12/145783

Inventors:

Feng Gao - Sunnyvale CA, US

Assignee:

KONICA MINOLTA SYSTEMS LABORATORY, INC. - Huntington Beach CA

International Classification:

G06F 3/12

US Classification:

358 115

Abstract:

A batch file printing method is described. A user opens a file using an application, and issues a print request. From the print dialog box, the user chooses to set printing preferences. The print preferences dialog box includes tabs for setting various printing references, and an additional batch file printing tab for selecting a number of files to be printed as the same batch using the same printing preferences. The batch file printing tab includes a file list box showing the files to be included in the batch and buttons allowing the user to add files to or remove files from the list. The selected files, along with the currently open file, are printed at once using the same printing preferences set by the user. The selected files may be in different folders, and may be different type of files.