Feng F Gao

US Patent:

6486081, Nov 26, 2002

Filed:

Nov 24, 1999

Appl. No.:

09/449203

Inventors:

Tetsuya Ishikawa - Santa Clara CA
Padmanabhan Krishnaraj - Mountain View CA
Feng Gao - Mountain View CA
Alan W. Collins - San Francisco CA
Lily Pang - Fremont CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 2131

US Classification:

438788, 438787, 438789, 438792

Abstract:

The present invention provides an apparatus for depositing a film on a substrate comprising a processing chamber, a substrate support member disposed within the chamber, a first gas inlet, a second gas inlet, a plasma generator and a gas exhaust. The first gas inlet provides a first gas at a first distance from an interior surface of the chamber, and the second gas inlet provides a second gas at a second distance that is closer than the first distance from the interior surface of the chamber. Thus, the second gas creates a higher partial pressure adjacent the interior surface of the chamber to significantly reduce deposition from the first gas onto the interior surface. The present invention also provides a method for depositing a FSG film on a substrate comprising: introducing first gas through a first gas inlet at a first distance from an interior surface of the chamber, and introducing a second gas through a second gas inlet at a second distance from the interior surface of the chamber, wherein the second gas creates a higher partial pressure adjacent the interior surface of the chamber to prevent deposition from the first gas on the interior surface. Alternatively, the first gas is introduced at a different angle from the second gas with respect to a substrate surface.

US Patent:

6660662, Dec 9, 2003

Filed:

Jan 26, 2001

Appl. No.:

09/771203

Inventors:

Tetsuya Ishikawa - Santa Clara CA
Alexandros T. Demos - San Ramon CA
Feng Gao - Mountain View CA
Kaveh F. Niazi - Santa Clara CA
Michio Aruga - Inba-Gun, JP

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 2144

US Classification:

438787, 438680, 438681, 438788

Abstract:

A method is provided for depositing a thin film on a substrate in a process chamber with reduced incidence of plasma charge damage. A process gas containing a precursor gases suitable for forming a plasma is flowed into a process chamber, and a plasma is generated from the process gas to deposit the thin film on the substrate. The precursor gases are flowed into the process chamber such that the thin film is deposited at the center of the substrate more rapidly than at an edge of the substrate.

US Patent:

6814814, Nov 9, 2004

Filed:

Mar 29, 2002

Appl. No.:

10/109736

Inventors:

Alan W. Collins - San Francisco CA
Feng Gao - Fremont CA
Tetsuya Ishikawa - Santa Clara CA
Padmanaban Krishnaraj - San Francisco CA
Yaxin Wang - Fremont CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

B08B 312

US Classification:

134 1, 134 11, 134 221, 134 22, 134 30, 134 56 R, 134 951, 134166 R, 216 37, 216 67, 216 71, 438714, 438905, 438906

Abstract:

In a method of cleaning process residues formed on surfaces in a substrate processing chamber, a sacrificial substrate comprising a sacrificial material is placed in the chamber, a sputtering gas is introduced into the chamber, and the sputtering gas is energized to sputter the sacrificial material from the substrate. The sputtered sacrificial material reacts with residues on the chamber surfaces to clean them. In one version, the sacrificial substrate comprises a silicon-containing material that when sputtered deposits silicon on the chamber walls that reacts with and cleans fluorine-containing species that are left behind by a chamber cleaning process.

US Patent:

6927993, Aug 9, 2005

Filed:

Aug 14, 2003

Appl. No.:

10/642079

Inventors:

Bomy Chen - Cupertino CA, US
Kai Man Yue - Yuen Long, HK
Dana Lee - Santa Clara CA, US
Feng Gao - Sunnyvale CA, US

Assignee:

Silicon Storage Technology, Inc. - Sunnyvale CA

International Classification:

G11C017/00

US Classification:

365104, 365 94

Abstract:

A array of multi-bit Read Only Memory (ROM) cells is in a semiconductor substrate of a first conductivity type with a first concentration. Each ROM cell has a first and second regions of a second conductivity type spaced apart from one another in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. Each ROM cell has one of a plurality of N possible states, where N is greater than 2. The state of each ROM cell is determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost. The array of ROM cells are arranged in a plurality of rows and columns, with ROM cells in the same row having their gates connected together.

US Patent:

6992909, Jan 31, 2006

Filed:

Jun 20, 2005

Appl. No.:

11/157318

Inventors:

Bomy Chen - Cupertino CA, US
Kai Man Yue - Yuen Long N.T., HK
Dana Lee - Santa Clara CA, US
Feng Gao - Sunnyvale CA, US

Assignee:

Silicon Storage Techtology, Inc. - Sunnyvale CA

International Classification:

G11C 17/00

US Classification:

365 94, 365104, 438527

Abstract:

A array of multi-bit Read Only Memory (ROM) cells is in a semiconductor substrate of a first conductivity type with a first concentration. Each ROM cell has a first and second regions of a second conductivity type spaced apart from one another in the substrate. A channel is between the first and second regions. The channel has three portions, a first portion, a second portion and a third portion. A gate is spaced apart and is insulated from at least the second portion of the channel. Each ROM cell has one of a plurality of N possible states, where N is greater than 2. The state of each ROM cell is determined by the existence or absence of extensions or halos that are formed in the first portion of the channel and adjacent to the first region and/or in the third portion of the channel adjacent to the second region. These extensions and halos are formed at the same time that extensions or halos are formed in MOS transistors in other parts of the integrated circuit device, thereby reducing cost. The array of ROM cells are arranged in a plurality of rows and columns, with ROM cells in the same row having their gates connected together.

US Patent:

7036453, May 2, 2006

Filed:

Sep 8, 2003

Appl. No.:

10/658350

Inventors:

Tetsuya Ishikawa - Santa Clara CA, US
Alexandros T. Demos - San Ramon CA, US
Feng Gao - Mountain View CA, US
Kaveh F. Niazi - Santa Clara CA, US
Michio Aruga - Inba-Gun, JP

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

C23C 16/00

US Classification:

118723R, 118715, 438787, 438788

Abstract:

A method is provided for depositing a thin film on a substrate in a process chamber with reduced incidence of plasma charge damage. A process gas containing a precursor gases suitable for forming a plasma is flowed into a process chamber, and a plasma is generated from the process gas to deposit the thin film on the substrate. The precursor gases are flowed into the process chamber such that the thin film is deposited at the center of the substrate more rapidly than at an edge of the substrate.

US Patent:

7242051, Jul 10, 2007

Filed:

May 20, 2005

Appl. No.:

11/134540

Inventors:

Yuniarto Widjaja - San Jose CA, US
John W. Cooksey - Brentwood CA, US
Changyuan Chen - Sunnyvale CA, US
Feng Gao - Sunnyvale CA, US
Ya-Fen Lin - Santa Clara CA, US
Dana Lee - Santa Clara CA, US

Assignee:

Silicon Storage Technology, Inc. - Sunnyvale CA

International Classification:

H01L 29/788

US Classification:

257316, 257317, 257319, 257E29129, 257E293

Abstract:

A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type in the substrate with a second region of the second conductivity type in the substrate, spaced apart from the first region. A continuous first channel region is defined between the first region and the second region. A plurality of floating gates are spaced apart from one another with each positioned over a separate portion of the channel region. A plurality of control gates are provided with each associated with and adjacent to a floating gate. Each control gate has two portions: a first portion over a portion of the channel region and a second portion over the associated floating gate and capacitively coupled thereto.

US Patent:

7247907, Jul 24, 2007

Filed:

May 20, 2005

Appl. No.:

11/134557

Inventors:

Feng Gao - Sunnyvale CA, US
Ya-Fen Lin - Santa Clara CA, US
John W. Cooksey - Brentwood CA, US
Changyuan Chen - Sunnyvale CA, US
Yuniarto Widjaja - San Jose CA, US
Dana Lee - Santa Clara CA, US

Assignee:

Silicon Storage Technology, Inc. - Sunnyvale CA

International Classification:

H01L 29/788

US Classification:

257315, 257316, 257321, 257324, 257326, 438201, 438257, 438258

Abstract:

A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type and a second region of the second conductivity type in the substrate, spaced apart from the first region, thereby defining a channel region therebetween. A plurality of floating gates are spaced apart from one another and each is insulated from the channel region. A plurality of control gates are spaced apart from one another, with each control gate insulated from the channel region. Each of the control gate is between a pair of floating gates and is capacitively coupled to the pair of floating gates. A plurality of select gates are spaced apart from one another, with each select gate insulated from the channel region. Each select gate is between a pair of floating gates.