Gong-Jong Yeh

US Patent:

7737808, Jun 15, 2010

Filed:

Aug 20, 2008

Appl. No.:

12/194542

Inventors:

Ching-Chao Huang - San Jose CA, US
Gong-Jong Yeh - San Jose CA, US
Clement Kam Lam Luk - San Jose CA, US
Tatsuya Arai - Los Altos CA, US

Assignee:

Hirose Electric - Cupertino CA

International Classification:

H01P 1/00

US Classification:

333260, 333245, 43960707

Abstract:

A connector has data signal conductors for communicating data signals and voltage reference (power and ground) conductors for the signals' return currents. Voltage reference conductors carrying the same voltage level are coupled together at one or more points between the ends of the connector to shift the connector's resonant frequency beyond an operating frequency range of the data signals. Decoupling capacitors may alternatively or additionally be inserted between pairs of voltage reference conductors carrying high and low voltage levels at one or more points between the ends of the connector to shift the connector's resonant frequency beyond an operating frequency range of the data signals.

US Patent:

59111496, Jun 8, 1999

Filed:

Nov 1, 1996

Appl. No.:

8/742339

Inventors:

Chung-Chen Luan - Saratoga CA
Siu-Ming Chong - Fremont CA
James H. Wang - San Jose CA
John Wong - Oakland CA
Gong-Jong Yeh - San Jose CA

Assignee:

NEC Electronics Inc. - Santa Clara CA

International Classification:

G06F 1200
G06F 1320
G06F 1336

US Classification:

711147

Abstract:

A computer system having a processor and at least one peripheral has a programmable shared memory system and method that selectively dedicates a first potion of memory to use by the processor and allocates a second portion of memory to shared use by the processor and any peripherals in the system. The programmable memory architecture is implemented using a dual bus architecture having a first-bus connected to the processor and a second bus coupled to the processor by a system controller and to the peripherals by a peripheral controller. The programmable memory architecture additionally has a configuration controller coupled to each configurable memory bank in the system. Each configuration controller is additionally coupled to both the first and second buses. Under programmed control, the each configuration controller couples the associated memory to either the first or second bus, responsive to configuration information stored in the system controller. Memory coupled to the first bus operates as dedicated processor memory and memory coupled to the second bus operates as shared memory, accessible by the processor and any peripherals in the system.