Hui Li Lu

US Patent:

20040049745, Mar 11, 2004

Filed:

Sep 6, 2002

Appl. No.:

10/236840

Inventors:

Mohammed Rahman - Santa Clara CA, US
Langya Yang - Sunnyvale CA, US
Yongjun Zhang - Sunnyvale CA, US
Victor Leung - Sunnyvale CA, US
Hui Lu - Sunnyvale CA, US
Shunjiang Xu - Sunnyvale CA, US
Rambabu Pyapali - Cupertino CA, US
Peter Lai - San Jose CA, US
Chin-Chang Wu - Saratoga CA, US

Assignee:

Sun Microsystems, Inc.

International Classification:

G06F017/50

US Classification:

716/004000

Abstract:

The present invention describes a method and an apparatus for waiving noise violations during semiconductor integrated circuit design. The noise violations in a circuit area (e.g., an individual cell, block of cells or the like) are identified using a threshold look-up table. The threshold look-up table includes different thresholds for each circuit area. The threshold look-up table is generated using various cell related information including practical noise handling limits of each cell that can be higher than traditional noise limits. The information in the threshold look-up table helps eliminate benign noise violations and a new noise report is generated. The new noise report incorporates the practical noise handling capabilities of the cell under analysis and identifies actual noise violations in the semiconductor integrated circuit.

US Patent:

7149956, Dec 12, 2006

Filed:

Feb 9, 2004

Appl. No.:

10/708095

Inventors:

Hui Lu - Union City CA, US

Assignee:

Pericom Semiconductor Corp. - San Jose CA

International Classification:

H03M 7/16

US Classification:

714809, 341 97, 341 98, 377 34, 714819

Abstract:

An L-bit gray-code input value can change by more N bits at a time. The lower N bits of the input are stored as a received least-significant-bits (LSB) while the upper bits are stored as a received most-significant-bits (MSB). A stored register holds the corrected, stored MSB and LSB for use by the receiver. When the received and stored MSB's mis-match, the new MSB is stored and the stored LSB is generated so that the stored register contains the smallest possible value with the new MSB. When the received and stored MSB's match, the full L bits are compared. When the received word is larger than the stored word, the largest mis-matching bit in the LSB is found, and bits above this are copied from the received LSB to the stored register, while lower bits are generated to produce the lowest value. Repeating the process converges the result.

US Patent:

20220271254, Aug 25, 2022

Filed:

Jan 5, 2022

Appl. No.:

17/569384

Inventors:

- Cupertino CA, US
Michelle C. Sherrott - Santa Clara CA, US
Steven J. Brewer - Atlanta GA, US
Ping Kuen Daniel Tsang - Taoyuan, TW
KiBeom Kim - Cupertino CA, US
Hui Lu - Cupertino CA, US
Siddharth Harikrishna Mohan - Aurora IL, US

International Classification:

H01L 51/52

Abstract:

An electronic device may have a display such as an organic light-emitting diode (OLED) display. The OLED display may have an array of OLED pixels that each have OLED layers interposed between a cathode and an anode. The pixels may be microcavity OLED pixels having optical cavities. The optical cavities may be defined by a partially transparent cathode layer and a reflective anode structure. The distance between the partially transparent cathode layer and the reflective anode structure for a pixel may be selected such that light at the wavelength emitted by the pixel forms a standing wave between the anode and the cathode. The standing wave may have only one anti-node and the emissive layer for the pixel may be aligned with that one anti-node. To mitigate short circuits, a roughness reduction layer and/or short-circuit-reducing layer having a high sheet resistance may be formed between the anode the OLED layers.

US Patent:

20190067394, Feb 28, 2019

Filed:

Aug 27, 2018

Appl. No.:

16/114039

Inventors:

- Cupertino CA, US
Cheng Chen - San Jose CA, US
Chien Lu - New Taipei City, TW
Chih-Lei Chen - Tai Chung, TW
Chin Wei Hsu - Hsinchu, TW
Hui Lu - Cupertino CA, US
KiBeom Kim - Cupertino CA, US
Lun Tsai - Zhubei, TW
Meng-Huan Ho - San Jose CA, US
Nai-Chih Kao - Taoyuan, TW
Pei-Ling Lin - New Taipei City, TW
Rui Liu - San Jose CA, US
Shan-Jen Yu - Taoyuan, TW
Wendi Chang - Santa Clara CA, US
Yusuke Fujino - Taoyuan, TW

International Classification:

H01L 27/32
H01L 51/50
H01L 51/52
H01L 51/56
G09G 3/3225

Abstract:

A display may have an array of pixels formed from organic light-emitting diodes and thin-film transistor circuitry. Each pixel may include organic layers interposed between an anode and a cathode. The organic layers may emit out-coupled light that escapes the display and waveguided light that is waveguided within the organic layers. A reflector may be placed at the edge of the organic layers to reflect the waveguided light out of the display. The reflector may be located within a pixel definition layer and may be formed from metal or may be formed from one or more interfaces between high-refractive-index material and low-refractive-index material, The reflector may be formed from an extended portion of the pixel anode. The reflector may be formed from light-reflecting particles that are suspended in the pixel definition layer.

US Patent:

20180088866, Mar 29, 2018

Filed:

Sep 22, 2017

Appl. No.:

15/713144

Inventors:

- Shenzhen, CN
Hui LU - Santa Clara CA, US

International Classification:

G06F 3/06

Abstract:

This application provides a link management method. The physical device includes a first memory that stores a tail pointer of a link and a second memory that stores a head pointer of the link, and the physical device supports one time of enqueue processing and one time of dequeue processing in one clock cycle. The method includes: when a first link is not empty before the enqueue processing, modifying, by the physical device, a first tail pointer that is of the first link and that is in the first memory; and when a second link is not empty after the dequeue processing, modifying, by the physical device, a second head pointer that is of the second link and that is in the second memory.