Jan 2013 to 2000 Account Payable AssistantEmerson Accounting Services Falls Church, VA Jun 2011 to Aug 2011 Internship Entry Level Accountant
Education:
George Mason University Fairfax, VA May 2012 Bachelor of Science in AccountingNorthern Virginia Community College Annandale, VA May 2009 Bachelor of Science in Information Systems and Operations Management
Skills:
Proficient in Microsoft Office Suite, such as Word, Excel, Access, and PowerPoint. Competent in Visio, Microsoft Project, QuickBooks, and SBT Accounting System. Be able to type 70-75 words per minute. Bilingual English/Vietnamese. Solid analytical background and comfort with using data and information to create specific analyses. Quick learner, very detail-oriented and versatile. Great teamwork skills. Strong adaptability.
Emerson Accounting Services Falls Church, VA Jun 2011 to Aug 2011 Internship Entry Level Accountant
Education:
George Mason University Fairfax, VA 2009 to 2012 Bachelor of Science in AccountingGeorge Mason University Fairfax, VA 2009 to 2012 Bachelor of Science in Information Systems and Operations ManagementNorthern Virginia Community College Annandale, VA 2006 to 2009 Associate of Science in Accounting
Skills:
Proficient in Microsoft Word, Excel, Internet Explorer, Mozilla Firefox, Google Chrome, and internet-based research Competent in Microsoft Access, PowerPoint, Visio, Project Be able to type 60-75 words per minute Fluent in English and Vietnamese Analytical thinking, planning Accuracy and attention to details Adaptability
Us Patents
Test Structure For Characterizing Multi-Port Static Random Access Memory And Register File Arrays
Leland Chang - New York NY, US Jente B. Kuang - Austin TX, US Robert K. Montoye - New York NY, US Hung C. Ngo - Austin TX, US Kevin J. Nowka - Georgetown TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G11C 29/00
US Classification:
714718
Abstract:
A test structure for characterizing a production static random access memory (SRAM) array. The test structure includes a characterization circuit having multiple memory cell columns connected in series to form a ring configuration. The characterization circuit is fabricated on a wafer substrate in common with and proximate to a production SRAM array. The characterization circuit preferably includes SRAM cells having a circuit topology substantially identical to the circuit topology of memory cells within the production SRAM array. In one embodiment, the test structure is utilized for characterizing a multi-port memory array and includes multiple memory cell columns connected in series to form a ring oscillator characterization circuit. Each cell column in the characterization circuit includes multiple SRAM cells each having a latching node and multiple data path access nodes. Selection control circuitry selectively enables the multiple data path access nodes for the SRAM cells within the characterization circuit.
Test Structure For Characterizing Multi-Port Static Random Access Memory And Register File Arrays
Leland Chang - New York NY, US Jente B. Kuang - Austin TX, US Robert K. Montoye - New York NY, US Hung C. Ngo - Austin TX, US Kevin J. Nowka - Georgetown TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G11C 29/00
US Classification:
714718
Abstract:
A test structure for characterizing a production static random access memory (SRAM) array. The test structure includes a characterization circuit having multiple memory cell columns connected in series to form a ring configuration. The characterization circuit is fabricated on a wafer substrate in common with and proximate to a production SRAM array. The characterization circuit preferably includes SRAM cells having a circuit topology substantially identical to the circuit topology of memory cells within the production SRAM array. In one embodiment, the test structure is utilized for characterizing a multi-port memory array and includes multiple memory cell columns connected in series to form a ring oscillator characterization circuit. Each cell column in the characterization circuit includes multiple SRAM cells each having a latching node and multiple data path access nodes. Selection control circuitry selectively enables the multiple data path access nodes for the SRAM cells within the characterization circuit.
System For And Method Of Emulating Electronic Input Devices
Anthony Russo - New York NY, US Frank Chen - San Jose CA, US Mark Howell - Glendale AZ, US Hung Ngo - San Jose CA, US Marcia Tsuchiya - Fremont CA, US David Weigand - Santa Clara CA, US
International Classification:
G06F 9/455
US Classification:
703024000
Abstract:
The system and method of the present invention is directed to emulating and configuring any of a plurality of electronic input devices. A system in accordance with one embodiment of the present invention comprises an interface and an emulator. The interface is for selecting and configuring an electronic input device from a plurality of electronic input devices, and the emulator is for emulating the electronic input device. Preferably, the plurality of electronic input devices comprise any two or more of a scroll wheel, a mouse, a joy stick, a steering wheel, an analog button, and a touch bar. Also in a preferred embodiment, the interface is an Application Programming Interface (API) and the emulator comprises a finger swipe sensor for receiving user input.