Hung N Ngo

US Patent:

6335650, Jan 1, 2002

Filed:

Sep 28, 2000

Appl. No.:

09/670829

Inventors:

David William Boerstler - Round Rock TX
Harm Peter Hofstee - Austin TX
Hung Cai Ngo - Austin TX
Kevin John Nowka - Round Rock TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03H 1126

US Classification:

327261, 327530

Abstract:

A method and apparatus for adjusting time delays in circuits with multiple operating supply voltages are disclosed. A voltage level detector and a delay means are coupled to a critical timing circuit of an integrated circuit capable of operating at multiple supply voltages. The voltage level detector detects a supply voltage at which the integrated circuit is operating. When the operating supply voltage of the integrated circuit changes from a first voltage level to a second voltage level, the voltage level detector sends a signal to the delay means and to a current enhancement circuit such that the delay means and current enhancement circuit can automatically modify the delay of the switching time of an output signal from the critical timing circuit.

US Patent:

6335900, Jan 1, 2002

Filed:

Dec 12, 2000

Appl. No.:

09/734226

Inventors:

Ohsang Kwon - Austin TX
Hung Cai Ngo - Austin TX
Kevin John Nowka - Round Rock TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 800

US Classification:

36523006, 36518911, 36518907

Abstract:

A method and apparatus for selectable word line boosting in a memory device provides operating of the memory device over wide power supply ranges. A voltage reference and a comparator determine whether or not the power supply voltage has dropped below the range in which word line boosting is not required. If the power supply voltage has dropped, word line boosting is enabled, improving the noise margin and access time of the memory when operating at lower voltages.

US Patent:

6345286, Feb 5, 2002

Filed:

Oct 30, 1998

Appl. No.:

09/182593

Inventors:

Sang Hoo Dhong - Austin TX
Hung Cai Ngo - Austin TX
Kevin John Nowka - Round Rock TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 750

US Classification:

708708, 708702, 708629

Abstract:

A 6-to-3 carry-save binary adder is disclosed. The 6-to-3 carry-save adder includes a means for receiving six data inputs and a means for simultaneously adding the six data inputs to generate a first data output, a second data output, and a third data output. The first data output is a SUM output, the second data output is a CARRY output, and the third data output is a CARRY output.

US Patent:

6360238, Mar 19, 2002

Filed:

Mar 15, 1999

Appl. No.:

09/270469

Inventors:

Sang Hoo Dhong - Austin TX
Kyung Tek Lee - Austin TX
Hung Cai Ngo - Austin TX
Kevin John Nowka - Round Rock TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 501

US Classification:

708205, 708211

Abstract:

A zero/one anticipator having an integrated sign selector is disclosed. A leading zeros string and a leading ones string are generated by examining carry propagates, generates, and kills of two adjacent bits of two input operands to an adder within a floating-point processor. The leading zeros string is for a positive sum, and the leading ones string is for a negative sum. A normalization shift amount is then determined from the leading zeros string and the leading ones string. A sign of a sum of the two input operands is then determined separately but concurrently with the normalization shift amount determination process. The sign is then utilized to select either the positive sum or the negative sum for a proper normalization shift amount.

US Patent:

6393446, May 21, 2002

Filed:

Jun 30, 1999

Appl. No.:

09/343450

Inventors:

Sang Hoo Dhong - Austin TX
Hung Cai Ngo - Austin TX
Jaehong Park - Austin TX
Joel Abraham Silberman - Somers NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 700

US Classification:

708209

Abstract:

A dual mode rotator capable of performing 32-bit and 64-bit rotation. According to a preferred embodiment, the dual mode rotator includes a first, second, and third rotator units wherein each rotator has a plurality of inputs and outputs. The inputs of the second rotator are operatively connected to the corresponding outputs of the first rotator unit. The inputs of the third rotator unit are operatively connected to the corresponding outputs of the second rotator. Responsive to selection of 32-bit rotation mode, the upper half of the inputs to the first rotator are zero and the lower half of the outputs of the third rotator are replicated in the upper half of the outputs of the third rotator.

US Patent:

6404235, Jun 11, 2002

Filed:

Aug 31, 2000

Appl. No.:

09/651959

Inventors:

Kevin J. Nowka - Round Rock TX
Hung Cai Ngo - Austin TX
Jieming Qi - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 19096

US Classification:

326 96, 326 95

Abstract:

A dynamic circuit having reduced dynamic node switching latency. The operating status of the dynamic circuit alternates between a pre-charge phase in which a pre-charge device charges the dynamic node, and an evaluation phase in which data at the input of the dynamic circuit may or may not precipitate a dynamic node discharge. Each evaluation phase may be characterized as including an initial standby interval prior to the evaluation discharge, followed by an evaluate interval over which the dynamic node completes an evaluation discharge. A standby device is utilized to drive an output of the dynamic circuit low during a pre-charge phase and to maintain the output low during an standby interval in which dynamic circuit inputs do not result in the dynamic node being discharged. The dynamic circuit includes a standby control circuit that disables the standby device during the evaluation interval, resulting in reduced dynamic node switching capacitance. The dynamic circuit may further include a keeper device connected in parallel with the pre-charge device, wherein the keeper device maintains the dynamic node charged during the standby interval of an evaluation phase.

US Patent:

6407574, Jun 18, 2002

Filed:

Sep 26, 2000

Appl. No.:

09/670436

Inventors:

Huajun Wen - Austin TX
Hung Cai Ngo - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 1716

US Classification:

326 21, 326 30, 326 86, 326 90, 326 17, 327170

Abstract:

Disclosed is a system for reducing propagation delays caused by capacitive coupling of RC interconnects. The system comprises a first interconnect utilized for propagating signals, a second interconnect also utilized for propagating signals but which propagates signals at a faster rate than the first interconnect, and a charge dumping circuit with an input coupled to a point on the second interconnect and an output coupled to a corresponding point on the first interconnect. The charge dumping circuit includes a pulse generation circuit and a select-signal generation circuit, both of which are utilized to enable charge to be dumped from the second interconnect to the first interconnect to increase switching times of the signals propagating on the first interconnect and improve overall propagation speed.

US Patent:

6483888, Nov 19, 2002

Filed:

Oct 11, 2001

Appl. No.:

09/974987

Inventors:

David W. Boerstler - Round Rock TX
Gary D. Carpenter - Pflugerville TX
Hung C. Ngo - Austin TX
Kevin J. Nowka - Round Rock TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 2100

US Classification:

377 47, 327115, 327117, 327159, 327415

Abstract:

A clock divider circuit receives a first clock signal and frequency divides the first clock signal to generate a second clock signal. The first and second clocks are inputs to multiplexer (MUX) that selects one of the clocks as the MUX output based on the state of a MUX control signal. The MUX output is combined with a latched Freeze clock signal in an AND gate to generate a clock output signal. The state of Bypass logic signal determines which clock signal is selected as the clock output signal. The Bypass logic signal is received in a latch circuit which latches the Bypass logic signal in two series latches one latch latching on the positive edge and one on the negative edge of the MUX output. The output of the second latch is latched in a third latch on when a NOR logic gate signals the first and second clock are concurrently at a logic zero assuring that the MUX output is changed only when both clocks are low. The clock output signal is gated with the latched Freeze clock signal in the AND logic gate.

Address:

2924 Bernardino Cv, Austin, TX 78728

VIN:

1N4AL2AP6AN461622

Make:

NISSAN

Model:

ALTIMA

Year:

2010