Jack Sing Lam

US Patent:

7893858, Feb 22, 2011

Filed:

Mar 5, 2009

Appl. No.:

12/398926

Inventors:

Pirooz Hojabri - San Jose CA, US
Jack Lam - San Jose CA, US

Assignee:

NetLogic Microsystems, Inc. - Santa Clara CA

International Classification:

H03M 1/34

US Classification:

341158, 341161

Abstract:

A method and apparatus for performing pipelined capacitive folding and interpolation analog-to-digital conversion. In one embodiment, the apparatus comprises a multistage pipelined analog-to-digital converter having: a distributed sample/hold and preamp, folding and interpolation unit which combines a plurality of preamplified signals using a capacitive folding and capacitive interpolation; and a decoding unit coupled to decode the output signals from the folding and interpolation unit. The distributed sample/hold and preamp drastically improves the input dynamic range and hence increases ADC over all linearity. This technique offers an inherent dynamic offset cancellation in every sample and can be implemented in submicron CMOS, using the core digital supply.

US Patent:

8063811, Nov 22, 2011

Filed:

Nov 18, 2010

Appl. No.:

12/949615

Inventors:

Pirooz Hojabri - San Jose CA, US
Jack Lam - San Jose CA, US

Assignee:

NetLogic Microsystems, Inc. - Santa Clara CA

International Classification:

H03M 1/34

US Classification:

341158, 341161

Abstract:

A method and apparatus for performing pipelined capacitive folding and interpolation analog-to-digital conversion. In one embodiment, the apparatus comprises a multistage pipelined analog-to-digital converter having: a distributed sample/hold and preamp, folding and interpolation unit which combines a plurality of preamplified signals using a capacitive folding and capacitive interpolation; and a decoding unit coupled to decode the output signals from the folding and interpolation unit. The distributed sample/hold and preamp drastically improves the input dynamic range and hence increases ADC over all linearity. This technique offers an inherent dynamic offset cancellation in every sample and can be implemented in submicron CMOS, using the core digital supply.