Jae Yeol Park

US Patent:

6616394, Sep 9, 2003

Filed:

Dec 30, 1998

Appl. No.:

09/223111

Inventors:

Jae Heon Park - Cupertino CA

Assignee:

Silicon Valley Group - San Jose

International Classification:

B65H 500

US Classification:

41422201, 414217, 414937

Abstract:

Systems and methods are described for wafer processing. A wafer processing apparatus includes: a first wafer transporter; a process station coupled to the first wafer transporter, the process station including: a first plurality of wafer processing stacks, each of the plurality of wafer processing stacks including a plurality of wafer processing modules, and a second wafer transporter coupled to the plurality of wafer processing modules, each of the plurality of wafer processing modules adjacent, and accessible by, the second wafer transporter; and a third wafer transporter coupled to the process station, wherein any of the plurality of wafer processing modules in any of the plurality of wafer processing stacks can be accessed by at least two adjacent wafer transporters from among the first, second and third wafer transporter. The systems and methods provide advantages from minimizing pre-process and/or post-process times, minimizing variation of the pre-process and/or post-process times and reducing robot over utilization.

US Patent:

6746826, Jun 8, 2004

Filed:

Jul 25, 2000

Appl. No.:

09/624712

Inventors:

Jae Heon Park - Cupertino CA
Jung Suk Bang - Kyumggi-do, KR

Assignee:

ASML Holding N.V.

International Classification:

G03C 500

US Classification:

430322, 430325, 430331

Abstract:

Methods and apparatus are described for improved yield and line width performance for liquid polymers and other materials. A method for minimizing precipitation of developing reactant by lowering a sudden change in pH includes: developing at least a portion of a polymer layer on a substrate with an initial charge of a developer fluid; then rinsing the polymer with an additional charge of the developer fluid so as to controllably minimize a subsequent sudden change in pH; and then rinsing the polymer with a charge of another fluid. A method for achieving a more uniform, quasi-equilibrium succession of states from the introduction of developer chemical to the wafer surface to its removal is also described. The method reduces process-induced defects and improves critical dimension (CD) control.

US Patent:

7004708, Feb 28, 2006

Filed:

Jul 11, 2003

Appl. No.:

10/618175

Inventors:

Jae Heon Park - Cupertino CA, US

Assignee:

ASML Holding N.V.

International Classification:

B65H 5/00

US Classification:

41422201, 414217, 414937

Abstract:

Systems and methods are described for wafer processin. A wafer processing apparatus includes: a first wafer transporter; a process station coupled to the first wafer transporter, the process station including: a first plurality of wafer processing stacks, each of the plurality of wafer processing stacks including a plurality of wafer processing modules, and a second wafer transporter coupled to the plurality of wafer processing modules, each of the plurality of wafer processing modules adjacent, and accessible by, the second wafer transporter; and a third wafer transporter coupled to the process station, wherein any of the plurality of wafer processing modules in any of the plurality of wafer processing stacks can be accessed by at least two adjacent wafer transporters from among the first, second and third wafer transporter. The systems and methods provide advantages from minimizing pre-process and/or post-process times, minimizing variation of the pre-process and/or post-process times and reducing robot over utilization.

US Patent:

7053485, May 30, 2006

Filed:

Aug 13, 2003

Appl. No.:

10/640177

Inventors:

Kyong-Mo Bang - Sunnyvale CA, US
Jae M. Park - San Jose CA, US

Assignee:

Tessera, Inc. - San Jose CA

International Classification:

H01L 23/04
H01L 23/544
H01L 23/34
H05K 1/00

US Classification:

257730, 257797, 257727, 361749

Abstract:

A microelectronic package is made by a process which includes folding a substrate. Alignment elements on different parts of the substrate engage one another during the folding process to position the parts of the substrate precisely relative to one another. One or more of the alignment elements may be a mass of an overmolding encapsulant covering a chip.

US Patent:

7176506, Feb 13, 2007

Filed:

Dec 24, 2003

Appl. No.:

10/746810

Inventors:

Masud Beroz - Livermore CA, US
Michael Warner - San Jose CA, US
Lee Smith - Frisco TX, US
Glenn Urbish - Coral Springs FL, US
Jae M. Park - San Jose CA, US
Yoichi Kubota - Pleasanton CA, US

Assignee:

Tessera, Inc. - San Jose CA

International Classification:

H01L 27/148

US Classification:

257232, 257723, 257E23066

Abstract:

A radio frequency chip package is formed by assembling a connecting element such as a circuit board or flexible circuit tape having chips thereon with a bottom plane element such as a lead frame incorporating a large thermally-conductive plate and leads projecting upwardly from the plane of the plate. The assembly step places the rear surfaces of the chips on the bottom side of the connecting element into proximity with the thermal conductor and joins the conductive traces on the connecting element with the leads. The resulting assembly is encapsulated, leaving terminals at the bottom ends of the leads exposed. The encapsulated assembly may be surface-mounted to a circuit board. The leads provide robust electrical connections between the connecting element and the circuit board.

US Patent:

7304376, Dec 4, 2007

Filed:

Jul 28, 2004

Appl. No.:

10/901407

Inventors:

Belgacem Haba - Cupertino CA, US
Jae M. Park - San Jose CA, US
Nicholas J. Colella - Pleasanton CA, US

Assignee:

Tessers, Inc. - San Jose CA

International Classification:

H01L 23/48

US Classification:

257696, 257722

Abstract:

A microelectronic element such as a semiconductor chip has springs such as coil springs bonded to contacts so that the springs serve as electrical connections to a circuit panel. The unit can be tested readily and can be surface-mounted to a circuit panel by bonding the distal ends of the springs, remote from the microelectronic element, to the panel. The springs can also serve as antennas so as to provide a miniaturized phased array.

US Patent:

7368695, May 6, 2008

Filed:

May 3, 2005

Appl. No.:

11/120711

Inventors:

Michael Estrella - San Jose CA, US
Jae M. Park - San Jose CA, US
Kenneth Robert Thompson - San Jose CA, US
Craig S. Mitchell - San Jose CA, US
Belgacem Haba - Cupertino CA, US

Assignee:

Tessera, Inc. - San Jose CA

International Classification:

H01L 27/00

US Classification:

2502081, 257434, 257680

Abstract:

An image sensor package is disclosed that reduces the overall size of known image sensor packages. The image sensor package includes an image sensor and image sensor controller that are arranged on a substrate so that the surfaces of the image sensor and image sensor controller are directly adjacent one another. A package in accordance with the present invention reduces the amount of space in the package by allowing at least one surface of the image sensor controller and at least one surface of the image sensor to be directly attached or connected to one another. Electrical conductive material in the nature of anisotropic conductive materials is also preferably applied to the substrate in the form of an adhesive layer to allow for the image sensor controller and the image sensor to be in electrical communication with one another.

US Patent:

7397068, Jul 8, 2008

Filed:

Dec 9, 2004

Appl. No.:

11/010077

Inventors:

Jae M. Park - San Jose CA, US

Assignee:

Tessera, Inc. - San Jose CA

International Classification:

H01L 33/00

US Classification:

257 88, 257 89, 257 98, 257 99, 257E33001

Abstract:

A light assembly for use with a low voltage power source. The light assembly semiconductor photo-emitters are electrically in series with a higher forward voltage drop than the associated low voltage power supply. To provide the necessary voltage the light assembly includes a current regulated step-up DC/DC converter. The semiconductor photo-emitters that are electrically in series are in the form of a monolithic light emitting diode array with a plurality of light emitting diode elements electrically and mechanically in series with a conductive, rigid bond region between the cathode region of the first light emitting diode element and the anode region of the second light emitting diode element. The first and second light emitting diode elements may differ in band gaps to emit different colors, that are additive to a non-primary color, such as white.

Address:

964 Mangrove Ave APT 21, Sunnyvale, CA 94086

Phone:

4085987941

VIN:

KNDJT2A52C7441013

Make:

KIA

Model:

SOUL

Year:

2012