James Bradley Steele

US Patent:

6385749, May 7, 2002

Filed:

Apr 1, 1999

Appl. No.:

09/283809

Inventors:

Swaroop Adusumilli - Tempe AZ
James Steele - Chandler AZ
David Cassetti - Tempe AZ

Assignee:

Koninklijke Philips Electronics N.V. (KPENV) - Eindhoven

International Classification:

G01R 3128

US Classification:

714733, 714 30, 714726, 714727

Abstract:

An arrangement controls an IC designed with multiple âcoreâ circuits, such as multiple CPUs, with each core circuit including its own TAP controller. According to one example embodiment, multiple test-access port (TAP) controllers coupled to a common interface are controlled by adapting each TAP controller to receive input signals, determine if the TAP controller is enabled, and generate status signals and test signals. An output circuit responds to the TAP controllers by outputting one of the test signals respectively provided by the multiple TAP controllers, and a link module is used to maintain one of the TAP controllers enabled at a given time. The above-embodiment is useful, for example, in connection with IC applications that require an increasing number of core circuits without increasing the circuit area of the IC and/or the number of IC pins, and can be implemented to avoid changing existing structures of TAP controllers.

US Patent:

6782466, Aug 24, 2004

Filed:

Nov 24, 1999

Appl. No.:

09/449273

Inventors:

James Crawford Steele - Chandler AZ
Desi Rhoden - Phoenix AZ
George Crouse - Chandler AZ

Assignee:

Koninklijke Philips Electronics N.V. - Eindhoven

International Classification:

G06F 1200

US Classification:

711209, 711 5, 711170

Abstract:

A memory access approach optimizes memory address mapping for accessing data in a virtual memory arrangement wherein multiple banks of data are opened at once. One specific implementation is directed to a process of accessing data in a plurality of addressable banks of memory cells. The process involves accessing the memory cells by addressing arrays in the banks via column and row bits, and directing the address and control signals so that the addressable column address and row address bits are selected with a lower order group of the address bits directed to select the column address bits, and the next highest group of the address bits directed to select bank address bits. The next highest group of the address bits are directed to select the row address bits.

US Patent:

20080043931, Feb 21, 2008

Filed:

Aug 1, 2006

Appl. No.:

11/497929

Inventors:

James C. Steele - Chandler AZ, US
Harold Downey - Tempe AZ, US

Assignee:

Acoustic Technologies, Inc. - Mesa AZ

International Classification:

H04M 3/22

US Classification:

379 2703

Abstract:

An audio processor for two way communication includes a signal generator for producing test signals coupled to selected test points in the audio processor. An echo canceling circuit and a voice detection circuit within the audio processor provide data representing the response of the audio processing circuit to said test signals. The test signals include a single tone signal and a sweep frequency signal. Data from the test is used for adjusting the audio processor according to the results of the tests.

US Patent:

20140059101, Feb 27, 2014

Filed:

Aug 27, 2012

Appl. No.:

13/595071

Inventors:

James C. Steele - Chandler AZ, US

Assignee:

QUICKFILTER TECHNOLOGIES, LLC - Allen TX

International Classification:

G06F 17/10

US Classification:

708300

Abstract:

A method of performing an infinite-impulse response digital filter includes switching address pointers between a first instance of the filter and a second instance of the filter; where the first and second instances represent the same filter. A first instance of the filter executes operations sequentially multiplying a current input data value, and first and second previous input data values, with corresponding ones of a first set of filter coefficients, using a multiplier; and a second instance of the filter executes operations sequentially multiplying first and second previous intermediate data values with corresponding ones of a second set of filter coefficients, using the multiplier. Switching between first and second instances of the filter occurs at each data input value or frame according to an alternating signal.

US Patent:

20140081627, Mar 20, 2014

Filed:

Sep 14, 2012

Appl. No.:

13/620664

Inventors:

Ed Rocha - Mesa AZ, US
James Steele - Chandler AZ, US
Justin Allen - Mesa AZ, US

Assignee:

QUICKFILTER TECHNOLOGIES, LLC - Allen TX

International Classification:

G10L 19/00

US Classification:

7042001, 704E19001

Abstract:

A method for optimizing multiple psychoacoustic effects in a sound system includes synthesizing a high-frequency restored version of a input signal; adding the high-frequency restored version of the input signal to the input signal to create a second signal; synthesizing a third signal having enhanced spatialization from the second signal; synthesizing a fourth signal having virtual bass from the second signal; and, adding the third and fourth signals, or second, third and fourth signals, together to create an output signal.

US Patent:

63113023, Oct 30, 2001

Filed:

Apr 1, 1999

Appl. No.:

9/283648

Inventors:

David Cassetti - Tempe AZ
James Steele - Chandler AZ
Swaroop Adusumilli - Tempe AZ

Assignee:

Philips Semiconductor, Inc. - Sunnyvale CA

International Classification:

G01R 3128

US Classification:

714727

Abstract:

An arrangement controls an IC designed with multiple "TLM'ed core" circuits, such as multiple CPUs, with each core circuit including its own TAP controller and with multiple TAP controllers enabled a time. For applications typically requiring that control be transferred between such TAP controllers of various core circuits, one embodiment of the present invention expands a multiple "TLM'ed core" circuit design without changing the IEEE JTAG specification and without requiring more scan chains per TAP'ed core. One particular example embodiment includes each of the design's multiple cores including multiple test-access port (TAP) controllers, and including an internal TLM having a TLM register adapted to store a decodable instruction and a supplemental storage circuit adapted to store a coded signal. Also in the design, a chip-level TLM communicates with a common IEEE JTAG interface and with each of the multiple cores via the TLM register and the supplemental storage circuit. The chip-level TLM and the multiple cores signal use the supplemental storage circuit to indicate when instructions are to be transferred from a TLM'ed core to the chip-level TLM.

US Patent:

58156755, Sep 29, 1998

Filed:

Jun 13, 1996

Appl. No.:

8/670273

Inventors:

James C. Steele - Chandler AZ
Barry Davis - Phoenix AZ
Philip Wszolek - Phoenix AZ
Brian Fall - Chandler AZ
Swaroop Adusumilli - Tempe AZ
David Cassetti - Tempe AZ
Rodney Pesavento - Chandler AZ
Nick Richardson - Tempe AZ

Assignee:

VLSI Technology, Inc. - San Jose CA

International Classification:

G06F 1316

US Classification:

395293

Abstract:

A computer system in which a host bus is relieved from the burdens of data transfers between main memory and devices connected to an input/output (I/O) bus. Instead, the invention operates to place most of the burden of the data transfer on an internal bus within a bus arbitration unit so that the host bus is freed up much sooner than conventionally achieved. As a result, the computer system has substantially better performance because the host bus is available for other processing operations instead of being tied up with data transfers with devices (e. g. , peripheral devices) connected to the I/O bus.

US Patent:

57991782, Aug 25, 1998

Filed:

Apr 19, 1996

Appl. No.:

8/634794

Inventors:

Gary Walker - Phoenix AZ
Mike Crews - Phoenix AZ
James Steele - Chandler AZ

Assignee:

VLSI Technology, Inc. - San Jose CA

International Classification:

G06F 104

US Classification:

395557

Abstract:

The present invention relates to a system and method for starting and maintaining a Central Processing Unit (CPU) clock even though the CPU clock is operating under a Clock Division Emulation (CDE) scheme. Break Events are broken into different groups with each group of Break Events being mapped to a particular programmable event timer. Each of the programmable event timers have an associated time limit which will keep the CPU clock running for a time commensurate with that group of Break Events. When a Break Event occurs, the programmable event timer associated with that particular Break Event will load the corresponding time limit into the programmable event timer. Once loaded, the programmable event timer will keep the CPU clock running during the entire time limit. Only after all of the programmable event timers have counted down will the CPU clock be allowed to stop.