James K Yamaguchi

US Patent:

6784547, Aug 31, 2004

Filed:

Nov 21, 2002

Appl. No.:

10/302680

Inventors:

Angel Antonio Pepe - Irvine CA
James Satsuo Yamaguchi - Laguna Niguel CA

Assignee:

Irvine Sensors Corporation - Costa Mesa CA

International Classification:

H01L 2348

US Classification:

257758, 257635, 257737, 257778, 438106, 438107, 438108, 438109, 438123, 438124, 438125, 438126, 438127, 438613

Abstract:

A pre-formed integrated circuit chip is encapsulated into an electronic package, by forming an interconnect assembly separately from the pre-formed integrated circuit chip. If the interconnect assembly tests good it is bonded to the prepared integrated circuit chip. The interconnect assembly is flip bonded to the chip. The interconnect assembly and chip are passivated or potted into an integral structure to provide the electronic package. At least one test pad is defined in an interconnect layer, which test pad can be accessed and electrically connected on opposing sides of the test pad. The chip is underfilled with an insulating material to remove all voids between the chip and the interconnect assembly. The integrated circuit chip is then thinned. The test pad is accessed to test the chip.

US Patent:

6797537, Sep 28, 2004

Filed:

Oct 30, 2001

Appl. No.:

09/938686

Inventors:

Angel Antonio Pepe - Irvine CA
James Satsuo Yamaguchi - Laguna Niguel CA

Assignee:

Irvine Sensors Corporation - Costa Mesa CA

International Classification:

H01L 2144

US Classification:

438108, 438112, 438124, 438126, 438127

Abstract:

A pre-formed integrated circuit chip is encapsulated into an electronic package, by forming an interconnect assembly separately from the pre-formed integrated circuit chip. If the interconnect assembly tests good it is bonded to the prepared integrated circuit chip. The interconnect assembly is flip bonded to the chip. The interconnect assembly and chip are passivated or potted into an integral structure to provide the electronic package. At least one test pad is defined in an interconnect layer, which test pad can be accessed and electrically connected on opposing sides of the test pad. The chip is underfilled with an insulating material to remove all voids between the chip and the interconnect assembly. The integrated circuit chip is then thinned. The test pad is accessed to test the chip.

US Patent:

7239012, Jul 3, 2007

Filed:

Sep 28, 2004

Appl. No.:

10/951990

Inventors:

Angel Pepe - Rancho Palos Verdes CA, US
James Yamaguchi - Laguna Niguel CA, US

Assignee:

Irvine Sensors Corp. - Costa Mesa CA

International Classification:

H01L 23/02
H01L 23/58
H01L 23/48

US Classification:

257686, 257 48, 257737, 257777, 257778

Abstract:

A pre-formed integrated circuit chip-containing module formed from layers is disclosed. Each layer contains an integrated circuit chip that is encapsulated into an electronic package, by forming an interconnect assembly separately from the pre-formed integrated circuit chip. If the interconnect assembly tests good it is bonded to the prepared integrated circuit chip. The interconnect assembly is flip bonded to the chip. The interconnect assembly and chip are passivated or potted into an integral structure to provide the electronic package. At least one test pad is defined in an interconnect layer, which test pad can be accessed and electrically connected on opposing sides of the test pad. The chip is underfilled with an insulating material to remove all voids between the chip and the interconnect assembly. The integrated circuit chip is then thinned. The test pad is accessed to test the chip.

US Patent:

7335576, Feb 26, 2008

Filed:

Aug 5, 2005

Appl. No.:

11/197828

Inventors:

Ludwig David - Irvine CA, US
James Yamaguchi - Laguna Niguel CA, US
Stuart Clark - Newport Beach CA, US
W. Eric Boyd - San Clemente CA, US

Assignee:

Irvine Sensors Corp. - Costa Mesa CA

International Classification:

H01L 21/00

US Classification:

438462, 257E21599

Abstract:

A preprocessed semiconductor substrate such as a wafer is provided with a metal etch mask which defines singulation channels on the substrate surface. An isotropic etch process is used to define a singulation channel with a first depth extending into the semiconductor substrate material. A second anisotropic etch process is used to increase the depth of the singulation channel while providing substantially vertical singulation channel sidewalls. The singulation channel can be extended through the depth of the substrate or, in an alternative embodiment, a predetermined portion of the inactive surface of the substrate removed to expose the singulation channels. In this manner, semiconductor die can be precisely singulated from a wafer while maintaining vertical die sidewalls.

US Patent:

RE43877, Dec 25, 2012

Filed:

Feb 25, 2010

Appl. No.:

12/712810

Inventors:

David Ludwig - Irvine CA, US
James Yamaguchi - Laguna Niguel CA, US
Stewart Clark - Newport Beach CA, US
W. Eric Boyd - Irvine CA, US

Assignee:

Aprolase Development Co., LLC - Wilmington DE

International Classification:

H01L 21/00

US Classification:

438462, 438110, 438742, 438464, 257E21599

Abstract:

A preprocessed semiconductor substrate such as a wafer is provided with a metal etch mask which defines singulation channels on the substrate surface. An isotropic etch process is used to define a singulation channel with a first depth extending into the semiconductor substrate material. A second anisotropic etch process is used to increase the depth of the singulation channel while providing substantially vertical singulation channel sidewalls. The singulation channel can be extended through the depth of the substrate or, in an alternative embodiment, a predetermined portion of the inactive surface of the substrate removed to expose the singulation channels. In this manner, semiconductor die can be precisely singulated from a wafer while maintaining vertical die sidewalls.

US Patent:

8609473, Dec 17, 2013

Filed:

Oct 12, 2011

Appl. No.:

13/271797

Inventors:

Peter Lieu - Irvine CA, US
James Yamaguchi - Laguna Niguel CA, US
Randy Bindrup - Trabucco Canyon CA, US
W. Eric Boyd - La Mesa CA, US

Assignee:

ISC8 Inc. - Costa Mesa CA

International Classification:

H01L 21/00

US Classification:

438127, 438 15, 438 16, 438 17, 438109, 438114, 438118, 438459, 438613, 257737, 257790, 257E21502, 257E21529, 32475704, 32475705, 32476202, 32476206

Abstract:

A method for fabricating a stackable integrated circuit layer and a device made from the method are disclosed. A stud bump is defined on the contact pad of an integrated circuit die and the stud-bumped die encapsulated in a potting material to define a potted assembly. A predetermined portion of the potting material is removed whereby a portion of the stud bump is exposed. One or more electrically conductive traces are defined on the layer surface and in electrical connection with the stud bump to reroute the integrated circuit contacts to predetermined locations on the layer to provide a stackable neolayer.

US Patent:

20100291735, Nov 18, 2010

Filed:

Jul 27, 2010

Appl. No.:

12/844555

Inventors:

Volkan Ozguz - Aliso Veijo CA, US
Angel Pepe - Rancho Palos Verdes CA, US
James Yamaguchi - Laguna Niguel CA, US
W. Eric Boyd - San Clemente CA, US
Douglas Albert - Yorba Linda CA, US
Andrew Camien - Costa Mesa CA, US

International Classification:

H01L 21/70
H01L 21/60

US Classification:

438107, 438122, 257E21506, 257E21499, 257E21532

Abstract:

A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations on each die on the wafer at the reticle level using a series of semiconductor processing steps. The wafer is passivated and the vias are filled with a conductive material. The bond pads on the die are exposed and a metallization reroute from the user-selected bond pads and vias is applied. The wafer is then segmented to form thin, stackable layers that can be stacked and vertically electrically interconnected using the conductive vias, forming high-density electronic modules which may, in turn, be further stacked and interconnected to form larger more complex stacks.

US Patent:

20110031982, Feb 10, 2011

Filed:

Aug 4, 2010

Appl. No.:

12/806127

Inventors:

John Leon - Anaheim Hills CA, US
James Yamaguchi - Laguna Niguel CA, US
Volkan Ozguz - Aliso Viejo CA, US
W. Eric Boyd - Irvine CA, US

Assignee:

Irvine Sensors Corporation - Costa Mesa CA

International Classification:

G01R 27/28
H02H 3/08
H05K 7/00

US Classification:

324649, 361 931, 361783

Abstract:

A device and method are disclosed comprising one or more electrically conductive nano-structures defined on one or more surfaces of a microelectronic circuit such as an integrated circuit die, microelectronic circuit package (such as a TSOP, BGA or other prepackaged IC) a stacked microelectronic circuit package, or on the surface of one or more layers in a stack of layers containing one or more ICs.In one embodiment, the electrically conductive nano-structure is in electrical connection with a monitoring circuit and acts as a “trip wire” to detect unauthorized tampering with the device or module. Such a monitoring circuit may include a power source such as an in-circuit or in-module battery and a “zeroization” circuit within the chip or package to erase the contents of a memory when the electrically conductive nano-structure is breached or altered. The device may be configured to blow one or more fuses or overcurrent protection devices when the electrically conductive nano-structure is breached or altered.In a further embodiment, one or more electrically conductive nano-structures are used to interconnect and reroute one or more electrical connections between one or more ICs (or dummy leads and vias) to create an “invisible” set of electrical connections on the chip or stack to obfuscate an attempt to reverse engineer the device, i.e., a set of connections that cannot be observed by standard test means such as by X-ray or conventional microscope.