Jane T Chiu

US Patent:

59172070, Jun 29, 1999

Filed:

Feb 14, 1997

Appl. No.:

8/800663

Inventors:

Michael J. Colwell - Fremont CA
Jane C.T. Chiu - Sunnyvale CA
Abraham F. Yee - Cupertino CA
Stanley Wen-Chin Yeh - Fremont CA
Gobi R. Padmanabhan - Sunnyvale CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2182
H01L 2704
H01L 2710

US Classification:

257206

Abstract:

A gate array is disclosed having a programmable polysilicon layer which serves as both the gate electrodes for MOS transistors and routing lines for some connections between gate electrodes. The gate array structure is formed on a semiconductor substrate and has an array of identical base cells located in a core region of the structure. Each such base cell des the following elements: (1) a plurality of transistors, each of which includes a gate electrode; and (2) one or more gate connection strips formed on the substrate and electrically connecting selected gate electrodes of two or more of the transistors. Preferably, the gate connection strips are made from the same material as the selected gate electrodes (e. g. , polysilicon) and are integrally connected therewith. The gate connection strips may patterned (i. e.