Jason D Cain

US Patent:

7663766, Feb 16, 2010

Filed:

Sep 5, 2007

Appl. No.:

11/850072

Inventors:

Carsten Hartig - Meerane, DE
Jason P. Cain - Austin TX, US

Assignee:

Advanced Micro Devices, Inc. - Austin TX

International Classification:

G01B 11/24

US Classification:

356601, 3562372

Abstract:

A method includes collecting optical data from an unpatterned region including a first process layer. At least one optical parameter of the first process layer is determined based on the optical data associated with the unpatterned region. Optical data is collected from a patterned region including a second process layer. At least one characteristic of the patterned region is determined based on the optical data associated with the patterned region and the at least one optical parameter.

US Patent:

20090082897, Mar 26, 2009

Filed:

Sep 21, 2007

Appl. No.:

11/859204

Inventors:

Jason P. Cain - Austin TX, US
Bernd Schulz - Radebeul, DE

International Classification:

G06F 19/00

US Classification:

700121

Abstract:

A method includes generating a layout for an integrated circuit device. A plurality of metrology sites on the layout is generated. A metrology tag associated with each of the metrology sites is generated. Each metrology tag includes identification data, location data, and metrology context data relating to the associated metrology site. A system includes a data store and a metrology tag unit. The data store is operable to store a plurality of metrology tags. Each metrology tag is associated with a metrology site on a layout for an integrated circuit device and includes identification data, location data, and metrology context data relating to the associated metrology site. The metrology tag unit is operable to access at least a subset of the metrology tags and generate a metrology recipe for measuring characteristics of the integrated circuit device based on the subset of metrology tags.

US Patent:

20090144686, Jun 4, 2009

Filed:

Nov 30, 2007

Appl. No.:

11/948218

Inventors:

KEVIN R. LENSING - Austin TX, US
Jason P. Cain - Austin TX, US
Bhanwar Singh - Morgan Hill CA, US
Luigi Capodieci - Santa Cruz CA, US
Cyrus E. Tabery - San Jose CA, US

International Classification:

G06F 19/00

US Classification:

716 10

Abstract:

A method includes generating a layout for an integrated circuit device in accordance with a plurality of layout design rules. A plurality of metrology sites on the layout associated with at least one subset of the layout design rules is identified. A metrology tag associated with each of the metrology sites is generated. At least one metrology recipe for determining a characteristic of the integrated circuit device is generated based on the metrology tags. Metrology data is collected using the at least one metrology recipe. A selected layout design rule in the at least one subset is modified based on the metrology data.

US Patent:

20090144692, Jun 4, 2009

Filed:

Nov 30, 2007

Appl. No.:

11/948151

Inventors:

JASON P. CAIN - Austin TX, US
Kevin R. Lensing - Austin TX, US
Bhanwar Singh - Morgan Hill CA, US
Luigi Capodieci - Santa Cruz CA, US
Cyrus E. Tabery - San Jose CA, US

International Classification:

G06F 17/50

US Classification:

716 19

Abstract:

A method includes specifying a plurality of optical proximity correction metrology sites on a wafer. Metrology data is collected from at least a subset of the metrology sites. Data values are predicted for the subset of the metrology sites using an optical proximity correction design model. The collected metrology data is compared to the predicted data values to generate an optical proximity correction metric. A problem condition associated with the optical proximity correction design model is identified based on the optical proximity correction metric.

US Patent:

20100310972, Dec 9, 2010

Filed:

Jun 3, 2009

Appl. No.:

12/477474

Inventors:

Jason P. Cain - Austin TX, US

International Classification:

G03F 1/00
G03F 7/20
G03B 27/54

US Classification:

430 5, 430322, 355 67

Abstract:

A reticle includes a first pattern formed in a first die flash region of the reticle and a second pattern different than the first pattern formed in a second die flash region of the reticle. A method for patterning a wafer having a plurality of die regions defined thereon includes exposing a first die region using a first pattern formed on a reticle during a first exposure, repositioning the reticle, and exposing the first die region using a second pattern formed on the reticle during a second exposure.