Yuezhen Fan - San Jose CA, US Jason Xu - San Jose CA, US Stephen Wing-Ho Tang - San Jose CA, US Zhi-Min Ling - Cupertino CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G01R031/00
US Classification:
702117, 714723, 714724, 714725
Abstract:
Method and apparatus are disclosed for analyzing defect data produced in testing a semiconductor chip from a logic design. In various embodiments, input for processing is a first inspection data set that identifies a first set of physical locations that are associated with defects detected during fabrication of the chip. Also input is a second test data set that includes one or more identifiers associated with failing circuitry in the chip. A second set of physical locations is determined from the one or more identifiers of failing circuitry, hierarchical relationships between blocks of the design, and placement information associated with the blocks. Each of the one or more identifiers is associated with at least one of the blocks. Correspondences are identified between physical locations in the first inspection data set and the second set of physical locations.
Systems, apparatus, and methods of monitoring and reducing snore are discussed herein. Some embodiments may provide for a system including a snore detection module, a movement detection module, a control module, and an actuation module. The snore detection module may be configured to detect snore, such as by detecting vibrations caused by snoring. When snoring is detected, the control module may be configured to instruct the actuation module to apply stimulation to the user that is calibrated to cause the user to shift sleeping position without disturbing sleep. The movement detection module may be configured to monitor user movement. If the user fails to move in response to the actuation, the actuation module may increase the intensity of the actuation. If the user responds to the actuation, the process may be repeated after a predetermined delay to provide continuous snore monitoring and correction throughout user sleep.
University of Washington Seattle, WA Mar 2013 to Mar 2014 Research AssistantCypress Semiconductor Lynnwood, WA Jul 2013 to Sep 2013 Master's Circuit Design Co-opCypress Semiconductor Lynnwood, WA Jul 2012 to Sep 2012 Bachelor's Circuit Design Co-opCisco Systems, Inc San Jose, CA Jan 2011 to Jul 2011 Hardware Test Engineer Co-op
Education:
University of Washington Seattle, WA Dec 2014 M.S. in Electrical Engineering
Nov 2008 to 2000 Customer Service Representative / CashierCSUEB Department of Communication TV Studio / Lab Hayward, CA Oct 2007 to Jun 2008 Student AssistantDD's Discount San Leandro, CA Jul 2004 to Apr 2007 Customer Service Department Supervisor/Cashier
Education:
California State University East Bay Hayward, CA 2003 to 2008 BA in Mass Communication W/ Broadcasting Option
Treasurer of Tau Sigma Honor Society Apr 2011 to Mar 2012President of Campus Apartments Resident Association (CARA) Oct 2010 to Jan 2012Regnart Elementary School
Aug 2007 to Mar 2010 Special Education Volunteer Aide
Education:
DeAnza Community College Jun 2008 to Jun 2010 A.A. in Accounting