Jeff L Hunter

US Patent:

6990657, Jan 24, 2006

Filed:

Dec 3, 2001

Appl. No.:

09/998756

Inventors:

Jeff L. Hunter - Missouri City TX, US
Mark L. Buser - Green Brook NJ, US
Bruce W. C. Lee - Richmond Hill, CA
Imtaz Ali - Etobicoke, CA

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 9/44

US Classification:

717129, 717124, 717127, 717149, 711113, 711141, 711147, 711155

Abstract:

The invention relates to a method for maintaining coherency of software breakpoints in shared memory when debugging a multiple processor system. Using this method, at least two debug sessions associated with processors in the multiple processor system are activated. When a debug sessions sets a software breakpoint in a shared memory location, all active debug sessions are notified that the software breakpoint has been set. And, when a software breakpoint in shared memory is cleared by a debug session, all active debug sessions are notified that the software breakpoint has been removed.

US Patent:

7039901, May 2, 2006

Filed:

Dec 3, 2001

Appl. No.:

09/998329

Inventors:

Jeff L. Hunter - Missouri City TX, US
Mark L. Buser - Green Brook NJ, US
Bruce W. C. Lee - Richmond Hill, CA
Imtaz Ali - Etobicoke, CA

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 9/44
G06F 12/00

US Classification:

717124, 711141, 711147

Abstract:

The invention relates to a method for transparently maintaining cache coherency when debugging a multiple processor system with common shared memory. A software memory map representing the memory usage of the processors in the system to be debugged is created and in the software memory map is an indication of whether or not each processor has a cache. At least two debug sessions associated with two processors are activated. If an active debug session requests a write to a shared memory location, the request is executed and the software memory map is searched to located all processors having read access to that shared memory location. The write request is broadcast to each of the located processors so that each processor can perform any required cache updates.