Jeff Hunter

US Patent:

7007267, Feb 28, 2006

Filed:

Dec 3, 2001

Appl. No.:

09/998755

Inventors:

Jeff L. Hunter - Venetia PA, US
Mark L. Buser - Basking Ridge NJ, US
Bruce W. C. Lee - Richmond Hill, CA
Imtaz Ali - Etobicoke, CA

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 9/44

US Classification:

717124, 717149, 711141, 711147

Abstract:

The invention relates to a method for transparently writing to shared memory when debugging a multiple processor system. In this method, a software memory map reflecting the memory usage of the processors in the system to be debugged is created. Two or more debug sessions associated with processors in the system are activated. When a debug session makes a write request to a shared memory location, a check is made to see if the processor associated with that debug session has write access to the shared memory location. If it does, that processor is used to execute the write. If it does not, the software memory map is searched to find a processor that does have write access to the shared memory location and that processor is used to execute the write.

US Patent:

20020100020, Jul 25, 2002

Filed:

Dec 3, 2001

Appl. No.:

09/998330

Inventors:

Jeff Hunter - Venetia PA, US
Mark Buser - Basking Ridge NJ, US
Bruce Lee - Richmond Hill, CA
Imtaz Ali - Etobicoke, CA

International Classification:

G06F009/44

US Classification:

717/124000

Abstract:

The invention relates to a method for transparently maintaining cache coherency when debugging a multiple processor system with common shared memory. A software memory map representing the memory usage of the processors in the system to be debugged is created and in the software memory map is an indication of whether or not each processor has a cache. At least two debug sessions associated with two processors are activated. If an active debug session requests a write to a shared memory location, the request is executed and the software memory map is searched to located all processors having read access to that shared memory location. The write request is broadcast to each of the located processors so that each processor can perform any required cache updates.