Jeffery P Hunt

US Patent:

6483386, Nov 19, 2002

Filed:

Sep 29, 2000

Appl. No.:

09/676539

Inventors:

Daniel E. Cress - San Jose CA
Jeffery Scott Hunt - Ackerman MS

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

H03F 152

US Classification:

330298, 327309

Abstract:

An apparatus comprising a native device coupled to an input of an amplifier. The native device is configured to provide a high voltage protection in response to an enable signal.

US Patent:

7113445, Sep 26, 2006

Filed:

Sep 22, 2004

Appl. No.:

10/948006

Inventors:

Sanjay Sancheti - Sunnyvale CA, US
Jeffery Scott Hunt - Ackerman MS, US
George M. Ansel - Starkville MS, US

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

G11C 8/00

US Classification:

36523005, 365154

Abstract:

A multi-port memory cell () can be formed from seven transistors. Single ended write operations can be performed without a boosted word line voltage or variable power supply. A data value (D/DB) stored in the memory cell () can be cleared by shorting complementary data nodes (- and -) together. Write data can then be placed on a bit line. Complementary data nodes (- and -) can then be isolated once again, resulting in the write data being latched within the memory cell (). An access method () for a multi-port memory cell is also described.

US Patent:

56213387, Apr 15, 1997

Filed:

Jan 11, 1996

Appl. No.:

8/584105

Inventors:

Lin-Shih Liu - Fremont CA
Syed B. Raza - Sunnyvale CA
Hagop Nazarian - San Jose CA
George M. Ansel - Starkville MS
Stephen M. Douglass - Saratoga CA
Jeffery S. Hunt - Ackerman MS

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

H03K 19173
H03K 190948

US Classification:

326 46

Abstract:

A user configurable circuit contains clock logic, a switching element and a data path circuit. Input data is received in the switching element, and the switching element and the data path circuit constitute the entire data path for the circuit. A plurality of user configurable inputs are received to configure the circuit for a particular user application. The clock logic and the switching element implement a logic function that is configurable by the user configurable inputs. The logic function is pre-processed in the clock logic so that minimal delay occurs in the data path. In addition, the propagation delay through the switching element and the register is independent of the user configurable inputs. The user configurable circuit of the present invention has application for use as a macro cell for a programmable logic device permitting the user to configure the circuit as a D-type flip-flop, a T-type flip-flop. In addition, the user selects the polarity for the output circuit.

US Patent:

58645071, Jan 26, 1999

Filed:

Dec 18, 1996

Appl. No.:

8/769241

Inventors:

Andrew L. Hawkins - Santa Clara CA
Jeffery Scott Hunt - Ackerman MS
Satish C. Saripella - Starkville MS
Sanjay Sunder - Starkville MS

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

G11C 11401

US Classification:

36518906

Abstract:

The present invention concerns a method and apparatus for providing a dual level wordline clamp for use in a memory array. During a write operation, the clamp is at a level that ensures that a proper write margin is maintained. During a read operation, the clamp produces a lower level that reduces the overall current consumption of the circuit. During a write operation, the clamp also reduces the overall current consumption of the circuit. The present invention does not require complex reference circuits and, as a result, presents a minimal impact on die size.

US Patent:

55024033, Mar 26, 1996

Filed:

Dec 20, 1994

Appl. No.:

8/360469

Inventors:

Lin-Shih Liu - Fremont CA
Syed B. Raza - Sunnyvale CA
Hagop Nazarian - San Jose CA
George M. Ansel - Starkville MS
Stephen M. Douglass - Saratoga CA
Jeffery S. Hunt - Ackerman MS

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

H03K 19173
H03K 190948

US Classification:

326 46

Abstract:

A user configurable circuit contains clock logic, a switching element and a data path circuit. Input data is received in the switching element, and the switching element and the data path circuit constitute the entire data path for the circuit. A plurality of user configurable inputs are received to configure the circuit for a particular user application. The clock logic and the switching element implement a logic function that is configurable by the user configurable inputs. The logic function is pre-processed in the clock logic so that minimal delay occurs in the data path. In addition, the propagation delay through the switching element and the register is independent of the user configurable inputs. The user configurable circuit of the present invention has application for use as a macro cell for a programmable logic device permitting the user to configure the circuit as a D-type flip-flop, a T-type flip-flop. In addition, the user selects the polarity for the output circuit.

US Patent:

59368942, Aug 10, 1999

Filed:

Jun 15, 1998

Appl. No.:

9/094786

Inventors:

Andrew L. Hawkins - Santa Clara CA
Jeffery Scott Hunt - Ackerman MS
Satish C. Saripella - Starkville MS
Sanjay Sunder - Starkville MS

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

G11C 1604

US Classification:

36518906

Abstract:

The present invention concerns a method and apparatus for providing a dual level wordline clamp for use in a memory array. During a write operation, the clamp is at a level that ensures that a proper write margin is maintained. During a read operation, the clamp produces a lower level that reduces the overall current consumption of the circuit. During a write operation, the clamp also reduces the overall current consumption of the circuit. The present invention does not require complex reference circuits and, as a result, presents a minimal impact on die size.