Jeffery K Hunt

US Patent:

6353336, Mar 5, 2002

Filed:

Mar 24, 2000

Appl. No.:

09/534663

Inventors:

David R. Lindley - Starkville MS
William G. Baker - Starkville MS
Jeffery Scott Hunt - Ackerman MS

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

H03K 190175

US Classification:

326 83, 326 16, 326 87, 327525

Abstract:

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a first output signal in response to one or more first input signals. The second circuit may be configured to generate a second output signal in response to one or more second input signals. The first and second output signals may be presented to a bond pad.

US Patent:

6388469, May 14, 2002

Filed:

Aug 13, 1999

Appl. No.:

09/373870

Inventors:

Jeffery Scott Hunt - Ackerman MS
Muthukumar Nagarajan - Starkville MS

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

H03K 190175

US Classification:

326 81, 326 83, 326 68

Abstract:

An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a first control signal and a second control signal in response to (i) a first input signal, (ii) a second input signal and (iii) a voltage control signal. The second circuit configured to generate (i) an output signal in response to the first and the second control signals and (ii) the voltage control signal in response to a pad voltage.

US Patent:

6473357, Oct 29, 2002

Filed:

Sep 29, 2000

Appl. No.:

09/675895

Inventors:

Junfei Fan - Mississippi State MS
Jeffery Scott Hunt - Ackerman MS
Daniel E. Cress - San Jose CA

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

G11C 800

US Classification:

36523005, 365154, 365190, 365204, 365220, 365221, 365239

Abstract:

An apparatus comprising a memory array having a first port and a one or more other ports and a control circuit configured to couple (i) a bitline of the first port to a corresponding bitline of the one or more other ports and (ii) a dataline of the first port to a corresponding dataline of the one or more other ports in response to the first port and the one or more other ports accessing a common address.

US Patent:

6490712, Dec 3, 2002

Filed:

Oct 4, 2000

Appl. No.:

09/684159

Inventors:

James Daniel Merchant - Starkville MS
Gordon Carskadon - Starkville MS
Brian P. Evans - Starkville MS
Jeffery Scott Hunt - Ackerman MS
Anup Nayak - Fremont CA
Andrew Wright - Mountain View CA

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

G06F 1750

US Classification:

716 12, 716 17, 716 18

Abstract:

A method and system for automatically identifying configuration cell addresses in a schematic hierarchy is disclosed. In one embodiment of the present invention, a memory cell (e. g. , a configuration bit) is identified in a schematic hierarchy. Next, this embodiment determines an address for the memory cell. Then, this embodiment determines a unique name for the memory cell. The name is comprised of a hierarchical logical name and a schematic path name. By traversing the schematic and using logical names, all addresses of configuration bits of a circuit design may be automatically determined. The process is repeated for each memory cell in the schematic. This embodiment stores the unique name of the configuration bit and the address of the configuration bit in a data structure.

US Patent:

6532524, Mar 11, 2003

Filed:

Mar 30, 2000

Appl. No.:

09/538822

Inventors:

Junfei Fan - Mississippi State MS
Jeffery Scott Hunt - Ackerman MS

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

G06F 1214

US Classification:

711168, 711163, 711173, 711131, 711150

Abstract:

An apparatus comprising a first compare circuit, a second compare circuit and a memory. The first compare circuit may be configured to present a first match signal in response to a first address and a second address. The second compare circuit may be configured to present a second match signal in response to the first match signal, a first write enable signal and a second write enable signal. The memory may also be configured to present the first and second write enable signals. In one example, the memory may be configured to store and retrieve data with zero waiting cycles in response to the second match signal.

US Patent:

6609243, Aug 19, 2003

Filed:

Aug 29, 2001

Appl. No.:

09/941352

Inventors:

Brian P. Evans - Starkville MS
Jeffery Scott Hunt - Ackerman MS

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

G06F 1750

US Classification:

716 16, 716 2, 716 5, 716 17

Abstract:

An apparatus comprising a first stage and a second stage. The first stage may comprise a first section and a second section. The second stage may be embedded between the first and second sections. The first and second stages may be configured to equalize signal paths between a plurality of inputs of the first stage and a plurality of outputs of the second stage.

US Patent:

6784717, Aug 31, 2004

Filed:

Aug 28, 2002

Appl. No.:

10/229481

Inventors:

Jeffery Scott Hunt - Ackerman MS
Scott Anthony Jackson - Starkville MS

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

H03K 508

US Classification:

327318, 327333, 326 62, 326 80

Abstract:

An input buffer system has an input clipping circuit. The input clipping circuit has a high voltage input and uses transistors all being the thin oxide type transistors. A high voltage detect circuit is coupled to the input clipping circuit. An input buffer circuit is coupled to the input clipping circuit and has a low voltage output range.

US Patent:

6801064, Oct 5, 2004

Filed:

Aug 27, 2002

Appl. No.:

10/228436

Inventors:

Jeffery Scott Hunt - Ackerman MS
Scott Anthony Jackson - Starkville MS

Assignee:

Cypress Semiconductor, Corp - San Jose CA

International Classification:

H03B 100

US Classification:

327112, 327333, 326 63, 326 83

Abstract:

A buffer includes a pull-up level shifter coupled to an input signal. A pull-down level shifter separate from the pull-up level shifter is coupled to the input signal. A driver is coupled to the pull-up level shifter and the pull-down level shifter.