Jennifer D Schuler

US Patent:

20140021606, Jan 23, 2014

Filed:

Jul 19, 2012

Appl. No.:

13/552788

Inventors:

Charles L. Arvin - Poughkeepsie NY, US
Wolfgang Sauter - Hinesburg VT, US
Jennifer D. Schuler - Wappingers Falls NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 21/768
H01L 23/485

US Classification:

257738, 438613, 257E23021, 257E21589

Abstract:

A solder structure for joining an IC chip to a package substrate, and method of forming the same are disclosed. In an embodiment, a structure is formed which includes a wafer having a plurality of solder structures disposed above the wafer. A ball limiting metallurgy (BLM) layer disposed beneath each of the solder structures, above the wafer. At least one of the plurality of solder structures has a first composition, and at least another of the plurality of solder structures has a second composition.

US Patent:

20140021607, Jan 23, 2014

Filed:

Jul 19, 2012

Appl. No.:

13/552792

Inventors:

Charles L. Arvin - Poughkeepsie NY, US
Eric D. Perfecto - Poughkeepsie NY, US
Wolfgang Sauter - Hinesburg VT, US
Jennifer D. Schuler - Wappingers Falls NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 23/48
H01L 21/50

US Classification:

257738, 438121, 257E23021, 257E21499

Abstract:

An integrated circuit (IC) chip including solder structures for connection to a package substrate, an IC chip package, and a method of forming the same are disclosed. In an embodiment, an IC chip is provided comprising a wafer having a plurality of solder structures disposed above the wafer. A ball limiting metallurgy (BLM) layer is disposed between each of the plurality of solder structures and the wafer. At least one of the plurality of solder structures has a first diameter and a first height, and at least one other solder structure has a second diameter and a second height. The differing heights and volumes of solder structures facilitate solder volume compensation for chip join improvement on the IC chip side rather than the package side.

US Patent:

20220304175, Sep 22, 2022

Filed:

Jun 6, 2022

Appl. No.:

17/805641

Inventors:

- Cupertino CA, US
Abhijeet Misra - Sunnyvale CA, US
Anthony D. Prescenzi - Half Moon Bay CA, US
Brian M. Gable - Los Gatos CA, US
Christopher D. Prest - San Francisco CA, US
Hoishun Li - San Jose CA, US
James A. Yurko - Saratoga CA, US
Lee E. Hooton - Massapequa NY, US
Michael B. Wittenberg - San Francisco CA, US
Richard H. Dinh - Saratoga CA, US
Jennifer D. Schuler - Mountain View CA, US

International Classification:

H05K 5/04
H05K 5/00
H05K 5/02

Abstract:

A component for an electronic device can include a pre-formed substrate comprising a first metal and an additively manufactured portion bonded to the pre-formed substrate. The additively manufactured portion can include a first portion comprising a second metal and defining a volume, the first portion having a first value of a material property, and a second portion disposed in the volume, the second portion having a second value of the material property that is different from the first value.

US Patent:

20160204028, Jul 14, 2016

Filed:

Mar 17, 2016

Appl. No.:

15/072685

Inventors:

- Armonk NY, US
- Corona CA, US
Nicholas A. Polomoff - White Plains NY, US
Jennifer D. Schuler - Wappingers Falls NY, US
Matthew E. Souter - Tustin CA, US
Christopher L. Tessler - Poughquag NY, US

International Classification:

H01L 21/768

Abstract:

A method of selectively locating a barrier layer on a substrate includes forming a barrier layer on a surface of the substrate. The barrier layer comprises of a metal element and a non-metal element. The barrier layer may also be formed from a metal element and non-metal element. The method further includes forming an electrically conductive film layer on the barrier layer, and forming a metallic portion in the electrically conductive film layer. The method further includes selectively ablating portions of the barrier layer from the dielectric layer to selectively locate place the barrier layer on the substrate.

US Patent:

20160118283, Apr 28, 2016

Filed:

Oct 28, 2014

Appl. No.:

14/525254

Inventors:

- Armonk NY, US
Harry D. Cox - Rifton NY, US
Jorge A. Lubguban - Ridgefield CT, US
Jennifer D. Schuler - Poughquag NY, US

International Classification:

H01L 21/683
B32B 38/10
B32B 37/18

Abstract:

A method for processing a semiconductor wafer where an electrostatic layer is located on a surface of a handling wafer is used so the surface of the handling wafer may be handled with machinery that uses an electrostatic chuck. The electrostatic layer may be manipulated to increase or decrease the conductivity, and may be removed to allow light to pass through the handling wafer.

US Patent:

20160118287, Apr 28, 2016

Filed:

Oct 28, 2014

Appl. No.:

14/525267

Inventors:

- Armonk NY, US
Harry D. Cox - Rifton NY, US
Brian M. Erwin - Lagrangeville NY, US
Jorge A. Lubguban - Ridgefield CT, US
Eric D. Perfecto - Poughkeepsie NY, US
Jennifer D. Schuler - Poughquag NY, US

International Classification:

H01L 21/683
H01L 21/66
B32B 7/12
B32B 9/04
B32B 17/06
H01L 21/302
H01L 21/268

Abstract:

A method for processing a semiconductor wafer where an opaque layer is located on a surface of a handling wafer is used so the surface of the handling wafer may be detected through optical sensors. The opaque layer may be modified, or oriented, to allow light to pass through unobstructed.

US Patent:

20150352476, Dec 10, 2015

Filed:

Jun 9, 2014

Appl. No.:

14/299444

Inventors:

- Armonk NY, US
Harry D. Cox - Rifton NY, US
Arthur G. Merryman - Hopewell Junction NY, US
Jennifer D. Schuler - Poughquag NY, US

International Classification:

B01D 39/12
H01L 21/02
G03F 7/42
B01D 39/06
B01D 39/20

Abstract:

A photoresist stripping tool includes a reservoir configured to contain photoresist stripping solution and a Pb filter comprising a filter element with Tin (Sn) exterior surfaces. A semiconductor wafer fabrication system includes a semiconductor wafer attached to the photoresist stripping tool that strips photoresist from the semiconductor wafer. A photoresist stripping processes includes stripping photoresist from a leaded semiconductor wafer with photoresist stripping solution within the photoresist stripping tool, filtering Lead Pb from the photoresist stripping solution with the Pb filter, and stripping photoresist from a lead-free semiconductor wafer with the filtered photoresist stripping solution.

US Patent:

20150357235, Dec 10, 2015

Filed:

Aug 18, 2015

Appl. No.:

14/828608

Inventors:

- Armonk NY, US
- Corona CA, US
Nicholas A. Polomoff - White Plains NY, US
Jennifer D. Schuler - Wappingers Falls NY, US
Matthew E. Souter - Tustin CA, US
Christopher L. Tessler - Poughquag NY, US

International Classification:

H01L 21/768

Abstract:

A method of selectively locating a barrier layer on a substrate includes forming a barrier layer on a surface of the substrate. The barrier layer comprises of a metal element and a non-metal element. The barrier layer may also be formed from a metal element and non-metal element. The method further includes forming an electrically conductive film layer on the barrier layer, and forming a metallic portion in the electrically conductive film layer. The method further includes selectively ablating portions of the barrier layer from the dielectric layer to selectively locate place the barrier layer on the substrate.