Jiansheng Te Xu

US Patent:

20200411435, Dec 31, 2020

Filed:

Jun 28, 2019

Appl. No.:

16/457712

Inventors:

- Santa Clara CA, US
Joodong PARK - Portland OR, US
Walid M. HAFEZ - Portland OR, US
Chia-Hong JAN - Portland OR, US
Jiansheng XU - Portland OR, US

International Classification:

H01L 23/528
H01L 21/768
H01L 23/522
H01L 23/532

Abstract:

An integrated circuit structure comprises a base and a plurality of metal levels over the base. A first metal level includes a first dielectric material. The first metal level further includes a first plurality of interconnect lines in the first dielectric material, wherein the first plurality of interconnect lines in the first metal level have variable widths from relatively narrow to relatively wide, and wherein the first plurality of interconnect lines have variable heights based on the variable widths, such that a relatively wide one of the first plurality of interconnect lines has a taller height from the substrate than a relatively narrow one of the first plurality of interconnect lines, and a shorter distance to a top of the first metal level.