Jie Z Ni

US Patent:

6640261, Oct 28, 2003

Filed:

Oct 27, 1999

Appl. No.:

09/428600

Inventors:

Jie Ni - Beaverton OR
Richard Reohr - Hillsboro OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 300

US Classification:

710 6, 710 29, 710 33, 709103, 709232, 709240, 712217, 711158

Abstract:

Briefly, in accordance with one embodiment of the invention, an apparatus includes an integrated circuit that has the capability to schedule transferring processes that have an individual identification number. At least a portion of each individual identification number is used to indicate the presence of each of the transfer processes. Briefly, in accordance with another embodiment of the invention, an integrated circuit having a scheduler of transfer processes, each of the transfer processes having an identification number. The scheduler is coupled to a memory array of bits, and a portion of each identification number is used as a portion of an address to the memory array of bits. Briefly, in accordance with yet another embodiment of the invention, a method of scheduling requests for the transfer of data where each request having an identification number. The identification number is used in addressing a bit in an array of bits and set to indicate the request for the transfer of data.

US Patent:

6680910, Jan 20, 2004

Filed:

Jun 26, 1998

Appl. No.:

09/105395

Inventors:

Jie Ni - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04L 1226

US Classification:

370235, 370253

Abstract:

Briefly, in accordance with one embodiment of the invention, a system includes: a network interface unit (NIU). The network interface unit (NIU) is adapted to monitor bandwidth utilization of the network interface unit and adjust the minimum interval for the transmission of a flow control packet, based, at least in part, on the bandwidth utilization determination. Briefly, in accordance with another embodiment of the invention, an apparatus includes at least one integrated circuit. The integrated circuit includes the capability, either alone or in combination with other integrated circuits, to monitor the receive rate utilization of a network interface unit and adjust the minimum interval for the transmission of a flow control frame, based, at least in part, on the receive rate utilization determined.

US Patent:

6728260, Apr 27, 2004

Filed:

Jan 31, 2003

Appl. No.:

10/355447

Inventors:

Jie Ni - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04L 1256

US Classification:

370465, 370466, 370467

Abstract:

Briefly, in accordance with one embodiment of the invention, a system includes: shared memory. The system includes the capability to transfer to a router processing unit a fragment of a received frame and a pointer to the fragment in shared memory. Briefly, in accordance with another embodiment of the invention, a method of transferring a fragment of a received frame includes the following. The received frame and the byte length of a fragment of the received frame are stored in shared memory. The fragment of the received frame having the byte length indicated and a pointer to the location of the fragment in shared memory are transferred. Briefly, in accordance with yet another embodiment of the invention, a switch-router includes at least one integrated circuit. The at least one integrated circuit includes the capability, alone or in combination with one or more other integrated circuits, to transfer to a router processing unit a fragment of a received frame and a pointer to the location of the fragment in a shared memory.

US Patent:

6775719, Aug 10, 2004

Filed:

Sep 28, 2000

Appl. No.:

09/671703

Inventors:

Brian M. Leitner - Hillsboro OR
Dominic J. Gasbarro - Forest Grove OR
Jie Ni - Portland OR
Tom E. Burton - Vancouver WA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1300

US Classification:

710 33, 710 51, 370399, 370463

Abstract:

A host system is provided with one or more host-fabric adapters installed therein for connecting to a switched fabric of a data network. The host-fabric adapter comprises a host interface arranged to interface a host memory of the host system; a serial interface arranged to receive and transmit data from said switched fabric; a Micro-Engine (ME) arranged to work on multiple tasks based on a Virtual Interface (VI) to support data transfers via the switched fabric, and configured to issue a host request to said host interface for a host transaction including an address and length of host data to be fetched from the host memory, and an End-Of-Cell (EOC) indicator which indicates that a cell has been built for transmission via the serial interface, and to begin working on a different task without waiting for the corresponding host response of the host request from the host interface; a Scheduler arranged to supply a request and a request VI number to said Micro-Engine (ME) for work; and a Request Comparator arranged to check the current VI that is being worked on by the Micro-Engine (ME), and to generate an acknowledgment ACK or a negative acknowledgment NACK to the Scheduler depending upon whether the request VI number is currently being worked on by the Micro-Engine (ME).

US Patent:

6885715, Apr 26, 2005

Filed:

Jul 29, 1998

Appl. No.:

09/124642

Inventors:

Jie Ni - Beaverton OR, US
Richard S. Jensen - Aloha OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04L007/00

US Classification:

375356

Abstract:

Briefly, in accordance with one embodiment of the invention, a method of synchronizing two ends of a bi-directional network communication path includes the following. A sequence of predetermined characters are repeatedly transmitted from an end of a bi-directional network communication path if reception is lost at that end. Synchronization or resynchronization occurs from both ends if the sequence of predetermined characters is received at the other end.

US Patent:

6928055, Aug 9, 2005

Filed:

Aug 5, 2003

Appl. No.:

10/635750

Inventors:

Jie Ni - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04L012/26

US Classification:

370235, 370253

Abstract:

Briefly, in accordance with one embodiment of the invention, a system includes: a network interface unit (NIU). The network interface unit (NIU) is adapted to monitor bandwidth utilization of the netrwork interface unit and adjust the minimum interval for the transmission of a flow control packet, based, at least in part, on the bandwidth utilization determination. Briefly, in accordance with another embodiment of the invention, an apparatus includes at least one integrated circuit. The integrated circuit includes the capability, either alone or in combination with other integrated circuits, to monitor the receive rate utilization of a network interface unit and adjust the minimum interval for the transmission of a flow control frame, based, at least in part, on the receive rate utilization determined.

US Patent:

7103683, Sep 5, 2006

Filed:

Oct 27, 2003

Appl. No.:

10/695006

Inventors:

Rajesh S. Madukkarumukumana - Portland OR, US
Jie Ni - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/12
G06F 13/10
G06F 13/00
G06F 12/00

US Classification:

710 52, 710 8, 710 11, 710 54, 710 64, 709228, 709235, 711100, 711147

Abstract:

Provided are a method, system, and article of manufacture, where in one embodiment of the method metadata related to a packet may be allocated in a host memory by a protocol processor, where the host memory may be comprised in a host that may be capable of being coupled to a network adapter. The metadata may be copied from the host memory to an adapter memory that may be associated with the network adapter. The copied metadata may be processed by the protocol processor.

US Patent:

7120708, Oct 10, 2006

Filed:

Jun 30, 2003

Appl. No.:

10/610660

Inventors:

William T. Futral - Portland OR, US
Jie Ni - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/28

US Classification:

710 26, 710 22, 710308

Abstract:

Apparatus and method for carrying out a DMA transfer wherein an address is written into a DMA register of a DMA controller specifying a memory location within a memory device at which either the parameters for a transfer of a block of data are provided or the status of the transfer of a block of data is to be written by the DMA controller.