Joanna J Liu

US Patent:

6449525, Sep 10, 2002

Filed:

Apr 25, 2000

Appl. No.:

09/558457

Inventors:

Joanna Liu - Los Altos CA
Zheng Xu - Foster City CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

G06F 1900

US Classification:

700121, 20419212

Abstract:

A multiple step process sputter deposits material of uniform thickness on stepped surfaces of an integrated circuit substrate such as the surfaces of a high aspect ratio via or a narrow trench. Material is first sputter deposited at the bottom of the opening at high pressure using a high power RF source connected to a coil in the deposition chamber to couple energy into the plasma. A high power RF bias is applied to the substrate, and a low power DC bias is applied to the sputtering target. The same parameters are repeated in a second step except that the high power RF bias on the substrate support is either reduced to a low power level or reduced to zero (by the end of the second step) to deposit on the lowest quarter of the sidewall of the opening. In a third step, no RF bias is applied to the pedestal remains and the pressure is reduced to a medium pressure state, resulting in a deposition on the second quarter of the sidewall of the opening. In a fourth step, the RF power coupled to the plasma is reduced to a low level, resulting in deposition on the third quarter of sidewall of the opening.

US Patent:

60802855, Jun 27, 2000

Filed:

Sep 14, 1998

Appl. No.:

9/152651

Inventors:

Joanna Liu - Los Altos CA
Zheng Xu - Foster City CA

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

C23C 1434

US Classification:

20419212

Abstract:

A multiple step process sputter deposits material of uniform thickness on stepped surfaces of an integrated circuit substrate such as the surfaces of a high aspect ratio via or a narrow trench. Material is first sputter deposited at the bottom of the opening at high pressure using a source of high power RF energy connected to a coil in the deposition chamber to couple energy into the plasma. A high power RF bias is applied to the substrate, and a low power DC bias is applied to the sputtering target. The same parameters are repeated in a second step except that the high power RF bias on the substrate support is either reduced to a low power level or reduced to zero (by the end of the second step) to deposit on the lowest quarter of the sidewall of the opening. In a third step, no RF bias is applied to the pedestal remains and the pressure is reduced to a medium pressure state, resulting in a deposition on the second quarter of the sidewall of the opening. In a fourth step, the RF power coupled to the plasma is reduced to a low level, resulting in deposition on the third quarter of sidewall of the opening.