Joel L Mitchell

US Patent:

6384467, May 7, 2002

Filed:

Mar 24, 2000

Appl. No.:

09/534651

Inventors:

Joel Mitchell - Austin TX
Fred Cumpian - Austin TX
Gary Pfeffer - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2900

US Classification:

257529, 257530, 438132

Abstract:

A method for forming a cavity ( ) to a structure such as a poly fuse ( ) with a deep etch process whereby a mask is formed over the structure a first dielectric layer ( ) and an etch partially through the first dielectric layer is performed. Next, a second dielectric layer ( ) is deposited and a second mask is formed for completing the etch to the structure. Finally, an etch through the second dielectric ( ) to an area at or near the structure is performed. A resultant device has non-etched second dielectric material on the sidewalls of the etch cavity.

US Patent:

6054340, Apr 25, 2000

Filed:

Jun 6, 1997

Appl. No.:

8/870286

Inventors:

Joel Mitchell - Austin TX
Fred Cumplan - Pflugerville TX
Gary Pfeffer - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2182

US Classification:

438132

Abstract:

A method for forming a cavity (30) to a structure such as a poly fuse (114) with a deep etch process whereby a mask is formed over the structure a first dielectric layer (23) and an etch partially through the first dielectric layer is performed. Next, a second dielectric layer (34) is deposited and a second mask is formed for completing the etch to the structure. Finally, an etch through the second dielectric (34) to an area at or near the structure is performed. A resultant device has non-etched second dielectric material on the sidewalls of the etch cavity 30.

US Patent:

59603062, Sep 28, 1999

Filed:

Dec 15, 1995

Appl. No.:

8/573171

Inventors:

Mark D. Hall - Austin TX
Gregory Steven Ferguson - Austin TX
Joel Patrick Mitchell - Austin TX
Johanes P. D. Suryanata - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2144
H01L 218238
H01L 214763

US Classification:

438612

Abstract:

A process for dry etching a passivation layer (42) of a semiconductor device is performed such that a low radio frequency (RF) power step is used when an underlying bond pad (22) is initially exposed and a high RF power step is used after the initial exposure. The process virtually eliminates or reduces the likelihood of bond pad (22) staining, particularly when a polyimide die coat layer (72) is subsequently formed over the semiconductor device (50).