John Gilbert Mcbride

US Patent:

6367055, Apr 2, 2002

Filed:

Apr 27, 1999

Appl. No.:

09/299996

Inventors:

John G McBride - Ft Collins CO

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1750

US Classification:

716 4, 716 2, 716 6, 716121

Abstract:

The present invention is generally directed to a system and method for efficiently evaluating a design quality of a circuit defined by a netlist. An inventive method includes the steps of creating an element data structure for each circuit element in the netlist, wherein the data structure of a given element defines a plurality of physical characteristics for the element, and creating a node data structure for each circuit node in the netlist, wherein the data structure of a given node defines a plurality of physical characteristics for the node. Thereafter, the method determines a TRUE/FALSE value for the physical characteristics for entries within both the element data structure and the node data structure. Finally, the method records the determined TRUE/FALSE values for later retrieval. An inventive system includes an element data structure for defining each circuit element in the netlist, wherein the data structure of a given element defines a plurality of characteristics for the element.

US Patent:

6367062, Apr 2, 2002

Filed:

Feb 18, 1999

Appl. No.:

09/252138

Inventors:

John G. McBride - Ft Collins CO

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1750

US Classification:

716 12, 716 6, 716 10, 326 38, 326 49

Abstract:

In accordance with one aspect of the invention, a method is provided for identifying multiple, series-connected pass FETs in an integrated circuit, by evaluating a current node in the netlist to determine whether the current node is a static gate input (or output). If the node is that of a pass gate input (or output), the method then identifies at least one pass FET that is channel-connected to the current node, and determines that an output node (input node) of the at least one pass FET is the same node as the current node. Thereafter, the method reassigns the current node to be an input node (output node) of the at least one pass FET, and repeats the foregoing steps (beginning with identifying at least one pass FET that is channel-connected to the current node). In accordance with another aspect of the present invention, a system is provided for identifying multiple, series-connected pass FETs in an integrated circuit by evaluating a netlist. Preferably, the system is implemented in software and includes various code segments for: identifying a current node that is at an endpoint of a series of pass FET devices, identifying at least one pass FET that is series connected to the current node, evaluating direction of the at least one pass FET device, and resetting a new âcurrent nodeâ to a channel node of the at least one pass FET that is opposite the previous âcurrent nodeâ.

US Patent:

6389578, May 14, 2002

Filed:

May 26, 1999

Appl. No.:

09/318988

Inventors:

John G McBride - Ft Collins CO

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1750

US Classification:

716 5, 716 4, 716 6

Abstract:

The present invention provides a method and apparatus for determining the strongest and weakest paths from a supply of a gate comprised in an integrated circuit to an output node of the gate and from ground to the output node of the gate. The apparatus comprises a computer capable of being configured to execute a rules checker program. When the rules checker program is executed by the computer, it analyzes information relating to the network and determines the strongest and weakest paths from the supply to the output node of the gate and from ground to the output node of the gate. The rules checker program calculates the effective widths of the PFET and NFET networks in the gate being evaluated and uses this information to determine the strongest and weakest paths from the supply to the output node of the gate and from ground to the output node of the gate. Once the strongest and weakest paths have been determined, information relating to the strongest and weakest paths is utilized by the rules checker to model the gate as an inverter having a single PFET and a single NFET. Two models are generated for this purpose.

US Patent:

6405347, Jun 11, 2002

Filed:

Jun 30, 1999

Appl. No.:

09/343624

Inventors:

John G McBride - Ft Collins CO

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1750

US Classification:

716 4, 716 5

Abstract:

In accordance with one aspect of the invention a method is provided for determining a minimum FET width for a feedback FET on a precharge node. In one embodiment, the method identifies the NFET (ignoring evaluation NFETs) of each NFET tree having the largest width value. then sums width the values of these largest NFETs in at least one NFET tree associated with the precharge node, to determine an effective NFET width (N) of NFETs in the at least one NFET tree. Then, the method computes a minimum value of a PFET width (P) for the feedback FET, for a specified N:P ratio (R), in accordance with the equation: P=N/R. In accordance with another aspect of the invention a method is provided for determining a maximum FET width for a feedback FET on a precharge node. In one embodiment, the method evaluates at least one NFET tree, in accordance with a second circuit model, to determine an effective NFET width (N). This evaluation includes computing an effective width value of each NFET tree, and determining which NFET tree has the largest effective width.

US Patent:

6434723, Aug 13, 2002

Filed:

May 26, 1999

Appl. No.:

09/318985

Inventors:

John G McBride - Ft Collins CO
Thomas N Indermaur - Denver CO

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1750

US Classification:

716 4, 716 5

Abstract:

The present invention is generally directed to a system and method for evaluating a very large scale integrated circuit design in a structured, hierarchical fashion. In accordance with one aspect of the invention, a method evaluates a first circuit portion for a variety of potential errors and generates a first list of potential errors identified in the first circuit portion. The method further includes the step of adding at least one of the potential errors to a waiver file. The method further includes the step of examining a second circuit portion for a variety of potential errors, except those errors listed in the waiver file. In one embodiment, the step of examining the second circuit portion may be executed in a variety of ways. In one embodiment, the step may be configured to evaluate the second circuit portion for a number of potential errors. For any error(s) so identified, the method may add the errors to an error listing that is to be reported.

US Patent:

6449578, Sep 10, 2002

Filed:

Jun 30, 1999

Appl. No.:

09/345655

Inventors:

John G McBride - Ft Collins CO

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1900

US Classification:

702119, 716 6, 702182

Abstract:

The present invention provides a method and apparatus for determining the RC delays of a network comprised in an integrated circuit. The apparatus comprises logic configured to execute a rules checker algorithm. The rules checker algorithm operates in conjunction with a static timing analyzer. The static timing analyzer reads a netlist. The rules checker algorithm utilizes information relating to the netlist to generate a Spice deck which defines a circuit to be simulated. In the Spice deck, the driver gates of the network are replaced with ramp function voltage sources. The Spice deck includes the parasitic resistances and capacitance associated with the network. Once the Spice deck has been generated, the rules checker program calls a Spice simulation routine, which simulates the circuit defined by the Spice deck. The Spice routine generates a Spice results file that comprises voltage waveform information relating to the simulation. The rules checker algorithm utilizes this waveform information to determine the RC delays of the network.

US Patent:

6480987, Nov 12, 2002

Filed:

Jan 31, 2000

Appl. No.:

09/494749

Inventors:

John G McBride - Ft Collins CO

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1750

US Classification:

716 5, 716 4

Abstract:

A coupling capacitance analysis logic allows the classification of capacitance in a hierarchical electronic design. The coupling capacitance analysis logic analyzes capacitance between signal lines and other signal lines, and analyzes capacitance between signal lines and the substrate on which the circuitry resides, between signal lines and transistor gates, and between signal lines and diffusion regions. Capacitances associated with child blocks within the hierarchical design are first analyzed and then brought up into higher levels of the design without the need to repeat the analysis performed in the lower level. In this manner, a complex hierarchical design may be effectively and efficiently analyzed. Once the design analysis is complete, the logic of the invention determines the amount of coupling capacitance attributable to each signal in the design with respect to each subject signal. Each signal will be analyzed as the subject signal and each signal affecting the subject signal will be a culprit signal.

US Patent:

6484295, Nov 19, 2002

Filed:

Aug 15, 2000

Appl. No.:

09/639614

Inventors:

John G McBride - Ft Collins CO
Jan Kok - Fort Collins CO

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1750

US Classification:

716 4, 716 5

Abstract:

An electrical rules checker system and method are provided to appraise tri-state logic connected to a selected node of an integrated circuit by evaluating a netlist. In accordance with one aspect of the invention, the method selects a circuit configuration to be identified. Next, the method identifies any of the circuit configurations at the node, and identifies any probable circuit configurations at the node. Then the method appraises the circuit configurations and the probable circuit configurations. In accordance with another aspect of the invention, a system is provided for appraising tri-state logic connected to a selected node of an integrated circuit. The system operates by evaluating a netlist at the node, and further includes a code segment for selecting a circuit configuration to be identified, a second code segment for identify any of the selected circuit configurations a given node in a netlist, and a third code segment configured to identify any probable circuit configurations at the node in a netlist. A fourth code segment appraises the identified circuit configurations and probable circuit configurations.