John L Mccollum

US Patent:

20140078830, Mar 20, 2014

Filed:

Aug 29, 2013

Appl. No.:

14/013339

Inventors:

John McCollum - Orem UT, US

Assignee:

Microsemi SoC Corp. - San Jose CA

International Classification:

G11C 16/10

US Classification:

36518521, 36518525

Abstract:

A method for performing auto-refresh of a SONOS memory in a field programmable gate array in a system, includes sensing an auto-refresh condition, selecting a memory segment that has not yet been refreshed, storing the contents of memory segment, erasing the memory cells in the memory segment, and reprogramming the memory cells in the memory segment, until all of the memory segments have been reprogrammed

US Patent:

20220262434, Aug 18, 2022

Filed:

May 4, 2022

Appl. No.:

17/736563

Inventors:

- Chandler AZ, US
Fethi Dhaoui - Mountain House CA, US
John L. McCollum - Orem UT, US
Fengliang Xue - San Jose CA, US

Assignee:

Microchip Technology Inc. - Chandler AZ

International Classification:

G11C 13/00
H01L 45/00

Abstract:

A ReRAM memory array includes ReRAM memory cells and a select circuit having two series-connected select transistors connected in series with a ReRAM device. When ReRAM memory cell(s) are selected for erasing, the bit line coupled to the ReRAM memory cell(s) to be erased is biased at a first voltage potential. The source line coupled to the ReRAM memory cell(s) to be erased is biased at a second voltage potential greater than the first voltage potential, the difference between the first voltage potential and the second voltage potential being sufficient to erase the ReRAM device. The gates of the series-connected select transistors coupled to the ReRAM memory cell(s) to be erased are supplied with positive voltage pulses. The gates of the series-connected select transistors coupled to the ReRAM memory cell(s) unselected for erasing are supplied with a voltage potential insufficient to turn them on.

US Patent:

20210125666, Apr 29, 2021

Filed:

Jan 2, 2021

Appl. No.:

17/140064

Inventors:

- Chandler AZ, US
Fethi Dhaoui - Mountain House CA, US
John L McCollum - Orem UT, US
Fengliang Xue - San Jose CA, US

Assignee:

Microchip Technology Inc. - Chandler AZ

International Classification:

G11C 13/00
H01L 45/00

Abstract:

A ReRAM memory cell includes a ReRAM device including a solid electrolyte layer disposed between a first ion-source electrode and a second electrode and a select circuit including two series-connected select transistors connected in series with the ReRAM device, each of the two series-connected select transistors having a gate connected to a separate control line.

US Patent:

20210073072, Mar 11, 2021

Filed:

Sep 30, 2019

Appl. No.:

16/588916

Inventors:

- Chandler AZ, US
John L. McCollum - Orem UT, US

Assignee:

Microchip Technology Inc. - Chandler AZ

International Classification:

G06F 11/10
G11C 16/26
G11C 16/08
G11C 16/10

Abstract:

A method for providing error correction for a memory array includes for each memory word stored in a data memory portion of the memory array having at least one bit error, storing in an error PROM error data identifying a memory address for the data word in the data memory portion, a bit position of each bit error, and correct bit data for each bit error, monitoring memory addresses presented to the data PROM, if a memory address presented to the data memory portion is an identified memory address, reading from the error PROM the bit position of each bit error and the correct bit data for each bit error, and substituting the correct bit data into each identified bit position of a sense amplifier reading data from the data memory portion.

US Patent:

20200327937, Oct 15, 2020

Filed:

May 7, 2019

Appl. No.:

16/405895

Inventors:

- Chandler AZ, US
Fethi Dhaoui - Mountain House CA, US
John L. McCollum - Orem UT, US
Fengliang Xue - San Jose CA, US

Assignee:

Microchip Technology Inc. - Chandler AZ

International Classification:

G11C 13/00
H01L 45/00

Abstract:

A ReRAM memory cell includes a ReRAM device including a solid electrolyte layer disposed between a first ion-source electrode and a second electrode and a select circuit including two series-connected select transistors connected in series with the ReRAM device, each of the two series-connected select transistors having a gate connected to a separate control line.

US Patent:

20200327938, Oct 15, 2020

Filed:

May 7, 2019

Appl. No.:

16/405936

Inventors:

- Chandler AZ, US
Fethi Dhaoui - Mountain House CA, US
Victor Nguyen - San Ramon CA, US
John L. McCollum - Orem UT, US

Assignee:

Microchip Technology Inc. - Chandler AZ

International Classification:

G11C 13/00

Abstract:

A method for programming a resistive random-access memory (ReRAM) cell includes passing a first current through the ReRAM device for a first period of time, the first current selected to create a leakage path through the ReRAM device, and after passing the first current through the ReRAM device passing a second current through the ReRAM device for a second period of time shorter than the first period of time, the second current selected to create a current path having a desired resistance through the leakage path through the ReRAM device.

US Patent:

20200286559, Sep 10, 2020

Filed:

Mar 25, 2019

Appl. No.:

16/363619

Inventors:

- San Jose CA, US
Fethi Dhaoui - Mountain House CA, US
Pavan Singaraju - San Jose CA, US
Victor Nguyen - San Ramon CA, US
John L. McCollum - Orem UT, US
Volker Hecht - Barsinghausen, DE

Assignee:

Microsemi SoC Corp. - San Jose CA

International Classification:

G11C 14/00
H01L 27/112
H01L 27/11
H01L 45/00
H01L 27/24
G06F 11/10
G11C 29/52

Abstract:

A single-event-upset (SEU) stabilized memory cell includes a latch portion including a cross-coupled latch, and at least one cross coupling circuit path in the latch portion including a first series-connected pair of vertical resistors.

US Patent:

20200090747, Mar 19, 2020

Filed:

Nov 24, 2019

Appl. No.:

16/693317

Inventors:

- San Jose CA, US
John L. McCollum - Orem UT, US

Assignee:

Microsemi SoC Corp. - San Jose CA

International Classification:

G11C 13/00
H01L 27/24
H01L 45/00
G11C 5/06

Abstract:

A method for programming a ReRAM cell including a ReRAM device connected in series with an access transistor includes biasing the ReRAM cell with a programming potential that configures the access transistor in a common-source configuration and applying at least one programming voltage pulse to a gate of the access transistor, the programming voltage pulse having a magnitude selected to limit programming current to a preselected value.