John M Mccollum

US Patent:

7285818, Oct 23, 2007

Filed:

Jun 15, 2005

Appl. No.:

11/155005

Inventors:

Fethi Dhaoui - Patterson CA, US
John McCollum - Saratoga CA, US
Vidyadhara Bellippady - Cupertino CA, US
Zhigang Wang - Sunnyvale CA, US

Assignee:

Actel Corporation - Mountain View CA

International Classification:

H01L 29/788

US Classification:

257316, 257317, 257321

Abstract:

A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

US Patent:

7342278, Mar 11, 2008

Filed:

May 18, 2007

Appl. No.:

11/750650

Inventors:

Fethi Dhaoui - Patterson CA, US
John McCollum - Saratoga CA, US
Zhigang Wang - Sunnyvale CA, US

Assignee:

Actel Corporation - Mountain View CA

International Classification:

H01L 29/788

US Classification:

257316, 257317, 257321

Abstract:

A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

US Patent:

7368789, May 6, 2008

Filed:

Jun 13, 2005

Appl. No.:

11/152018

Inventors:

Fethi Dhaoui - Patterson CA, US
John McCollum - Saratoga CA, US
Frank Hawley - Campbell CA, US
Leslie Richard Wilkinson - Cave Junction OR, US

Assignee:

Actel Corporation - Mountain View CA

International Classification:

H01L 29/76

US Classification:

257369, 257314

Abstract:

A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor.

US Patent:

7473960, Jan 6, 2009

Filed:

Oct 29, 2007

Appl. No.:

11/927265

Inventors:

Fethi Dhaoui - Patterson CA, US
John McCollum - Saratoga CA, US
Vidyadhara Bellippady - San Jose CA, US
William C. Plants - Campbell CA, US
Zhigang Wang - Sunnyvale CA, US

Assignee:

Actel Corporation - Mountain View CA

International Classification:

H01L 29/788

US Classification:

257316, 257317, 257321

Abstract:

A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

US Patent:

7501681, Mar 10, 2009

Filed:

Dec 21, 2007

Appl. No.:

11/962615

Inventors:

Fethi Dhaoui - Patterson CA, US
John McCollum - Saratoga CA, US
Vidyadhara Bellippady - Cupertino CA, US
Zhigang Wang - Sunnyvale CA, US

Assignee:

Actel Corporation - Mountain View CA

International Classification:

H01L 29/788

US Classification:

257316, 257317, 257321

Abstract:

A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

US Patent:

7538379, May 26, 2009

Filed:

Dec 16, 2005

Appl. No.:

11/303865

Inventors:

Fethi Dhaoui - Patterson CA, US
John McCollum - Saratoga CA, US
Vidyadhara Bellippady - Cupertino CA, US
William C. Plants - Campbell CA, US
Zhigang Wang - Sunnyvale CA, US

Assignee:

Actel Corporation - Mountain View CA

International Classification:

H01L 29/788

US Classification:

257316, 257317, 257321

Abstract:

A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

US Patent:

7538382, May 26, 2009

Filed:

Oct 29, 2007

Appl. No.:

11/927237

Inventors:

Fethi Dhaoui - Patterson CA, US
John McCollum - Saratoga CA, US
Vidyadhara Bellippady - San Jose CA, US
William C. Plants - Campbell CA, US
Zhigang Wang - Sunnyvale CA, US

Assignee:

Actel Corporation - Mountain View CA

International Classification:

H01L 29/788

US Classification:

257316, 257317, 257321

Abstract:

A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

US Patent:

7573093, Aug 11, 2009

Filed:

Oct 29, 2007

Appl. No.:

11/927282

Inventors:

Fethi Dhaoui - Patterson CA, US
John McCollum - Saratoga CA, US
Vidyadhara Bellippady - San Jose CA, US
William C. Plants - Campbell CA, US
Zhigang Wang - Sunnyvale CA, US

Assignee:

Actel Corporation - Mountain View CA

International Classification:

H01L 29/788

US Classification:

257316, 257317, 257321

Abstract:

A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.