John W Mccollum

US Patent:

7692972, Apr 6, 2010

Filed:

Jul 22, 2008

Appl. No.:

12/177680

Inventors:

Michael Sadd - Austin TX, US
Fethi Dhaoui - Patterson CA, US
George Wang - Sunnyvale CA, US
John McCollum - Saratoga CA, US

Assignee:

Actel Corporation - Mountain View CA

International Classification:

G11C 16/04

US Classification:

36518526, 36518911, 36518501, 365104

Abstract:

A split-gate memory cell, includes an n-channel split-gate non-volatile memory transistor having a source, a drain, a select gate over a thin oxide, and a control gate over a non-volatile gate material and separated from the select gate by a gap. A p-channel pull-up transistor has a drain coupled to the drain of the split-gate non-volatile memory transistor, a source coupled to a bit line, and a gate. A switch transistor has first and second source/drain diffusions, and a gate coupled to the drains of the split-gate non-volatile memory transistor and the p-channel pull-up transistor. An inverter has an input coupled to the second source/drain diffusion of the switch transistor, and an output. A p-channel level-restoring transistor has a source coupled to a supply potential, a drain coupled to the first source/drain diffusion of the switch transistor and a gate coupled to the output of the inverter.

US Patent:

7906805, Mar 15, 2011

Filed:

Aug 22, 2008

Appl. No.:

12/196978

Inventors:

Michael Sadd - Austin TX, US
Fethi Dhaoui - Patterson CA, US
John McCollum - Saratoga CA, US
Richard Chan - Los Altos CA, US

Assignee:

Actel Corporation - Mountain View CA

International Classification:

H01L 29/788

US Classification:

257316, 257317, 257E29129

Abstract:

An edgeless one-transistor flash memory array includes transistors that have two polysilicon gate layers that overlay an active region. The bottom polysilicon gate layer is electrically isolated. The memory is configured such that current passes from drain to source under the bottom polysilicon layer, such that it does not approach a field oxide region. An edgeless two-transistor programmable memory includes memory cells that have two active devices. Two polysilicon gate layers overlay two active regions and are shared between the two active devices. One of the devices is used to program and erase the cell while the other used as a programmable switch in a programmable logic device. The bottom polysilicon gate layer is electrically isolated. The memory is configured such that current passes from drain to source under the bottom polysilicon layer, such that it does not approach a field oxide region.