Jonathan L Liu

US Patent:

6353893, Mar 5, 2002

Filed:

May 24, 1999

Appl. No.:

09/317742

Inventors:

Christine Liu - Cupertino CA 95014
Jonathan Liu - Cupertino CA 95014
Constance Liu - Cupertino CA 95014

International Classification:

G06F 126

US Classification:

713323, 713320, 713324

Abstract:

A new and useful sleep mode indicator system for laptop computers provides efficient use of battery power. In sleep mode, this indicator system turns OFF the typical blinking LED during the user-specified periods of unavailability. For example, a computer in sleep does not need to use electricity to identify its sleep mode status while its user is also asleep or is otherwise unavailable. This indicator system collects periods of unavailability and turns OFF the blinking LED during those periods. Also, sometimes the user may intend to operate the computer during a previously specified period of unavailability. This is reflected by the computer not in sleep mode at the start of the period and later enters temporarily into the sleep mode inside that specified period. Assuming that being the case, the present invention skips the period of unavailability just for that day. Further, the indicator system is not turned OFF any more for the rest of the specified period for that particular day.

US Patent:

6539485, Mar 25, 2003

Filed:

Jul 6, 1999

Appl. No.:

09/347729

Inventors:

Jonathan Liu - Cupertino CA 95014
Christine Liu - Cupertino CA 95014

International Classification:

G06F 132

US Classification:

713323

Abstract:

Intelligence is added to a computer sleep mode indicator system. A method for an intelligent indicator system is provided to turn off the sleep mode status indicator of a computer during sleep mode when a user is known to be unavailable to monitor the indicator, for example, when the user is sleeping or having lunch. This embodiment also handles reasonable variations of user habits. Further, to account for a gradual change of user unavailability habits over time, this invention obtains and applies a user unavailability intelligence by dynamically modifying the beginning and the ending times of a specified user unavailability period based on user experience. One preferred method for dynamically modifying the beginning and ending times is by calculating the moving averages of the actual sleep mode entry and exit times that occurred within a pre-determined period from the specified beginning and ending times.

US Patent:

7143219, Nov 28, 2006

Filed:

Dec 31, 2002

Appl. No.:

10/335577

Inventors:

Sunil C. Chaudhari - Milpitas CA, US
Jonathan W. Liu - Campbell CA, US
Manan Patel - San Jose CA, US
Nicholas E. Duresky - San Jose CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/00

US Classification:

710111, 710117, 710121, 710243

Abstract:

A method and apparatus for controlling access to a plurality of resources based on multiple received requests is provided. The system includes a priority register configured to receive each individual request, determine a priority for the request, and transmit the request to a priority appropriate path. A first high priority arbiter receives and arbitrates among highest priority requests in a round robin manner to determine a high priority suggested grant vector. At least one lower priority arbiter receiving and arbitrating among lower priority requests in a round robin manner to determine at least one lower priority suggested grant vector. Grant circuitry passes the high priority suggested grant vector unless said grant circuitry receives a low priority indication, whereby the grant circuitry passes a lower priority grant vector.

US Patent:

7162564, Jan 9, 2007

Filed:

Jul 9, 2002

Appl. No.:

10/190851

Inventors:

Bapiraju Vinnakota - Fremont CA, US
Jonathan W. Liu - Campbell CA, US
Saurin Shah - Santa Clara CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 17/10
G06E 1/00
G06F 1/02

US Classification:

710308, 710 22, 709250

Abstract:

A network interface between an internal bus and an external bus architecture having one or more external buses includes an external interface engine and an internal interface. The external interface engine (EIE) is coupled to the external bus architecture, where the external interface engine communicates over the external bus architecture in accordance with one or more bus protocols. The internal interface is coupled to the external interface engine and the internal bus, where the internal interface buffers network data between the internal bus and the external bus architecture. In one embodiment, the internal interface includes an internal interface (IIE) coupled to the internal bus, where the IIE defines a plurality of queues for the network data. An intermediate memory module is coupled to the IIE and the EIE, where the intermediate memory module aggregates the network data in accordance with the plurality of queues.

US Patent:

7515766, Apr 7, 2009

Filed:

Sep 22, 2004

Appl. No.:

10/947852

Inventors:

Sreenath Kurupati - Santa Clara CA, US
Brian R. Nickerson - Hillsboro OR, US
Samuel Wong - Richmond Hill, CA
Sunil Chaudhari - Milpitus CA, US
Jonathan W. Liu - Campbell CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06K 9/40
G09G 5/36

US Classification:

382268, 345559

Abstract:

A method and apparatus for hardware-base edge handling in video post-processing. In one embodiment, the method includes the identification of at least one unstored input pixel required to compute an output pixel during output pixel computation. Once identified, a pixel value is generated for the at least one unstored input pixel according to a detected edge handling mode. The generation of the pixel value for the unstored input pixel is performed, in one embodiment, if a position of the unstored input pixel is outside a pixel frame boundary. For example, in one embodiment, for output pixel computation of a scaling operation, the frame boundaries include a left (top) edge and a right (bottom) edge for which input pixels required to compute output pixels at or near the frame boundaries do not exist. Other embodiments are described and claimed.

US Patent:

7965151, Jun 21, 2011

Filed:

Jun 2, 2009

Appl. No.:

12/477052

Inventors:

Jonathan Edward Liu - Milpitas CA, US
Giao Minh Pham - Milpitas CA, US

Assignee:

Power Integrations, Inc. - San Jose CA

International Classification:

H02M 3/335
H03K 7/08

US Classification:

332109, 363 2111

Abstract:

A pulse width modulator (PWM) includes a driver and a two-way integrator. The driver is coupled to output a first and a subsequent period of a PWM signal. Both the first and the subsequent periods include the PWM signal changing between first and second states. The two-way integrator is coupled to integrate an input current and coupled to generate a duty ratio signal in response to integrating the input current. The driver determines a duty factor of both the first and the subsequent periods by setting the PWM signal to the second state in response to the duty ratio signal. The two-way integrator includes a capacitor that integrates the input current during the first period by charging the capacitor and integrates the input current during the subsequent period by discharging the capacitor.

US Patent:

8202726, Jun 19, 2012

Filed:

Sep 24, 2009

Appl. No.:

12/566048

Inventors:

Jonathan Liu - Milpitas CA, US
Mark Thompson - Morgan Hill CA, US
Luis J. Maranga - Santa Clara CA, US
Floro Cataniag - Pittsburg CA, US
Simon S. Hsu - Palo Alto CA, US

Assignee:

Medimmune, LLC - Gaithersburg MD

International Classification:

C12N 5/00

US Classification:

435403, 4242041, 4242091

Abstract:

The present invention provides novel serum-free cell culture medium and methods for cultivating MDCK cells. In particular, non-tumorigenic MDCK cells. The present invention also provides methods for producing influenza viruses (e. g. , particularly cold-adapted, and/or temperature sensitive, and/or attenuated influenza viruses) that eliminate the need for a cell culture medium exchange step. The novel medium and methods are useful to grow influenza viruses, in cell culture to high titer. The present invention further provides purification methods for purifying influenza viruses with high overall recovery of live virus and result in levels of host cell DNA (HCD), host cell protein (HCP) and non-specific endonuclease (e. g. , Benzonase), which are below the specifications required by regulatory agencies. The immunogenic compositions can be used to actively immunize subjects or to generate antibodies for a variety of uses, including passive immunization and diagnostic immunoassays.

US Patent:

8357376, Jan 22, 2013

Filed:

Jan 5, 2010

Appl. No.:

12/652557

Inventors:

Jonathan Liu - Milpitas CA, US
Richard Schwartz - San Mateo CA, US
Mark Thompson - Morgan Hill CA, US
Luis Jorge Camilo Maranga - Santa Clara CA, US
Simon Sheng-Tsiung Hsu - Palo Alto CA, US
Mridul Ghosh - San Jose CA, US
Ajit Subramanian - Berkeley CA, US

Assignee:

Memimmune, LLC - Gaithersburg MD

International Classification:

A61K 39/145

US Classification:

4242091, 424 936, 4241841, 435803, 530413

Abstract:

The present invention relates to novel MDCK cells which can be to grow viruses, e. g. , influenza viruses, in cell culture to higher titer than previously possible. The MDCK cells can be adapted to serum-free culture medium. The present invention further relates to cell culture compositions comprising the MDCK cells and cultivation methods for growing the MDCK cells. The present invention further relates to methods for producing influenza viruses in cell culture using the MDCK cells of the invention.