Joseph J Kopanski

US Patent:

56173407, Apr 1, 1997

Filed:

Feb 3, 1995

Appl. No.:

8/382973

Inventors:

Michael W. Cresswell - Frederick MD
Richard A. Allen - Germantown MD
Joseph J. Kopanski - Takoma Park MD
Loren W. Linholm - Ijamsville MD

Assignee:

The United States of America as represented by the Secretary of Commerce - Washington DC

International Classification:

G01B 1127
G01D 1800

US Classification:

36457101

Abstract:

Imaging instruments for inspecting products, such as semiconductor chips, are calibrated by providing a reference test structure having features which can be located by electrical measurements not subject to tool-induced shift and wafer-induced shift experienced by the imaging instrument. The reference test structure is first qualified using electrical measurements, and is then used to calibrate the imaging instrument. The electrical measurements may be made by forcing a current between a plurality of spaced reference features and an underlying conductor, or may be made by capacitive, conductive, magnetic, or impedance-measuring techniques. Capacitive techniques may also be used to detect features not susceptible of resistance measurement, such as dielectric or insulative materials, or metallic structures not accessible for forcing a current therethrough. A series of test structure elements may be fabricated with one component of each being spaced at progressively greater distances from an arbitrary baseline, such that a null-overlay element may be identified.