Julie N Lam

US Patent:

20210066227, Mar 4, 2021

Filed:

Aug 28, 2019

Appl. No.:

16/553962

Inventors:

- Santa Clara CA, US
Zuhair Bokharey - Santa Clara CA, US
Don Templeton - Santa Clara CA, US
Brian Schieck - Santa Clara CA, US
Julie Lam - Santa Clara CA, US
Prashant Pathak - Santa Clara CA, US

International Classification:

H01L 23/00
H01L 21/66

Abstract:

An IC package including an integrated circuit die having a major surface and one or more solder bumps located on the major surface in at least one corner region of the major surface and a substrate having a surface, the surface including bump pads thereon. The major surface of the integrated circuit die faces the substrate surface, the one or more solder bumps are bonded to individual ones of the bump pads to thereby form a bond joint, the major surface of the integrated circuit die has a footprint area of at least about 400 mm. A ratio of a coefficient of thermal expansion of the substrate (CTE) to a coefficient of thermal expansion of the integrated circuit die (CTE) is at least about 3:1. A method of manufacturing an IC package is also disclosed.