Jun Xu

US Patent:

7293142, Nov 6, 2007

Filed:

Apr 19, 2004

Appl. No.:

10/827048

Inventors:

Jun Xu - Cupertino CA, US
Xiangrong Wang - Milpitas CA, US
Christopher H. Pham - Milpitas CA, US
Srinivas Goli - San Jose CA, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G06F 12/00

US Classification:

711124, 717124, 707206

Abstract:

Systems, methods, apparatus and software can be implemented to detect memory leaks with relatively high confidence. By analyzing memory blocks stored in a memory, implicit and/or explicit contingency chains can be obtained. Analysis of these contingency chains identifies potential memory leaks, and subsequent verification confirms whether the potential memory leaks are memory leaks.

US Patent:

7444582, Oct 28, 2008

Filed:

Aug 1, 2005

Appl. No.:

11/195087

Inventors:

Siu-Hung Fred Au - Fremont CA, US
Gregory Burd - San Jose CA, US
Zining Wu - Los Altos CA, US
Jun Xu - Sunnyvale CA, US
Ichiro Kikuchi - Yokohama, JP
Tony Yoon - San Jose CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

H03M 13/00

US Classification:

714784, 714780

Abstract:

Systems and methods are provided for implementing various aspects of a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. If the decision-codeword corresponds to an inner code and an RS code is the outer code, a soft-information map can process the soft-information for the decision-codeword to produce soft-information for a RS decision-codeword. A RS decoder can employ the Berlekamp-Massey algorithm (BMA), list decoding, and a Chien search, and can include a pipelined architecture. A threshold-based control circuit can be used to predict whether list decoding will be needed and can suspend the list decoding operation if it predicts that list decoding is not needed.

US Patent:

7454690, Nov 18, 2008

Filed:

Aug 1, 2005

Appl. No.:

11/195183

Inventors:

Siu-Hung Fred Au - Fremont CA, US
Gregory Burd - San Jose CA, US
Zining Wu - Los Altos CA, US
Jun Xu - Sunnyvale CA, US
Ichiro Kikuchi - Yokohama, JP
Tony Yoon - San Jose CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

H03M 13/00

US Classification:

714780, 714784, 714759

Abstract:

Systems and methods are provided for implementing list decoding in a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. The soft-information can be organized into an order of combinations of error events for list decoding. An RS decoder can employ a list decoder that uses a pipelined list decoder architecture. The list decoder can include one or more syndrome modification circuits that can compute syndromes in parallel. A long division circuit can include multiple units that operate to compute multiple quotient polynomial coefficients in parallel. The list decoder can employ iterative decoding and a validity test to generate error indicators. The iterative decoding and validity test can use the lower syndromes.

US Patent:

7487321, Feb 3, 2009

Filed:

Feb 15, 2005

Appl. No.:

11/058585

Inventors:

Manikam Muthiah - Dindigul, IN
Chandra Sekhar Putha - Thiruvanmiyur, IN
Jun Xu - Cupertino CA, US
Xiangrong Wang - Milpitas CA, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G06F 12/00

US Classification:

711170, 707205, 707206, 717124, 717127, 718104, 711124

Abstract:

Systems, methods, apparatus and software can be implemented to detect memory leaks with relatively high confidence. By analyzing memory blocks stored in a memory, implicit and/or explicit contingency chains can be obtained. Analysis of these contingency chains identifies potential memory leaks, and subsequent successive verification confirms whether the potential memory leaks are memory leaks.

US Patent:

7590923, Sep 15, 2009

Filed:

Aug 1, 2005

Appl. No.:

11/195403

Inventors:

Ichiro Kikuchi - Yokohama, JP
Siu-Hung Fred Au - Fremont CA, US
Gregory Burd - San Jose CA, US
Zining Wu - Los Altos CA, US
Jun Xu - Sunnyvale CA, US
Tony Yoon - San Jose CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

G06F 11/00
H03M 13/00

US Classification:

714780, 714784

Abstract:

Systems and methods are provided for implementing error identification and evaluation for a Reed-Solomon (RS) error-correction code (ECC) system. The BMA algorithm and/or list decoding may produce one or more error locator polynomials that are related to a decision-codeword. An accelerated Chien search can be used to more quickly evaluate the one or more error locator polynomial. If the accelerated Chien search identifies a valid error locator polynomial, a normal Chien search can be used to identify error locations, and Forney's algorithm or an equivalent technique can be used to evaluate the error values. A RS ECC decoder can include a computation circuit that evaluates an error locator polynomial or an error evaluator polynomial. The computation circuit can include computation components that receive the coefficients of the polynomials.

US Patent:

7590924, Sep 15, 2009

Filed:

Oct 23, 2008

Appl. No.:

12/256652

Inventors:

Siu-Hung Fred Au - Fremont CA, US
Gregory Burd - San Jose CA, US
Zining Wu - Los Altos CA, US
Jun Xu - Sunnyvale CA, US
Ichiro Kikuchi - Yokohama, JP
Tony Yoon - San Jose CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

H03M 13/00

US Classification:

714785, 714793

Abstract:

Systems and methods are provided for implementing list decoding in a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. The soft-information can be organized into an order of combinations of error events for list decoding. An RS decoder can employ a list decoder that uses a pipelined list decoder architecture. The list decoder can include one or more syndrome modification circuits that can compute syndromes in parallel. A long division circuit can include multiple units that operate to compute multiple quotient polynomial coefficients in parallel. The list decoder can employ iterative decoding and a validity test to generate error indicators. The iterative decoding and validity test can use the lower syndromes.

US Patent:

7721265, May 18, 2010

Filed:

Apr 2, 2004

Appl. No.:

10/817466

Inventors:

Jun Xu - Cupertino CA, US
Christopher H. Pham - Milpitas CA, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G06F 9/44
G06F 11/00

US Classification:

717127, 714 31, 714 46, 719320

Abstract:

Systems, methods, apparatus and software can be implemented to provide a debugger agent, either separate form or integrated into the script-based testing platform, to coordinate the selection, activation, and or/operation of debuggers suitable for a particular unit and program under test. Such a debugger agent can provide run time monitoring and debugging activities where previously not possible. The debugger agent is generally independent agent, in that it can work with a variety of types of test scripts, test script handlers, programming languages, and debuggers without customization. Moreover, implementation generally needs no code instrumentation.

US Patent:

7774675, Aug 10, 2010

Filed:

Jul 5, 2006

Appl. No.:

11/481141

Inventors:

Adina Matache - Mounatin View CA, US
Heng Tang - Sunnyvale CA, US
Gregory Burd - San Jose CA, US
Aditya Ramamoorthy - Santa Clara CA, US
Jun Xu - Milpitas CA, US
Zining Wu - Los Altos CA, US

Assignee:

Marvell International Ltd. - Hamilton

International Classification:

H03M 13/00

US Classification:

714755, 714786, 714788, 714763, 714762, 714801, 370206

Abstract:

A MIMO transmitter comprises a scrambler; an encoder parser responsive to the scrambler; a forward error correction encoder responsive to the encoder parser, wherein the encoder applies a parity check matrix derived from a base matrix; an interleaver responsive to the forward error correction encoder; a QAM mapping module responsive to the interleaver; an inverse fast Fourier transform module responsive to the QAM mapping module; and an output module responsive to the inverse fast Fourier transform module.

Address:

2385 Lindaire Ave, San Jose, CA 95128

VIN:

2HNYD28318H508223

Make:

ACURA

Model:

MDX

Year:

2008