Karl P Brummel

US Patent:

6564178, May 13, 2003

Filed:

Apr 13, 1999

Appl. No.:

09/290806

Inventors:

Karl P Brummel - Ft Collins CO

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 945

US Classification:

703 22, 703 17, 716 4, 712227, 714739, 702117

Abstract:

The present invention provides a method and apparatus for testing architectural compliance of processors wherein various types of cases requiring some structure can be simulated and a degree of randomness can be added to the case without destroying the structure of the case. The apparatus comprises a computer capable of being configured to execute a testing program. When the computer is executing the testing program, the computer generates instructions and simulates execution of the instructions in a processor. During simulation, the computer detects when simulation of an instruction has caused an event to occur in the processor. The computer identifies the event that has occurred and generates a list of atoms and stores the list in a memory device in communication with the computer. Each of the atoms in the list corresponds to a description of a particular event handler task to be performed by the processor in response to the occurrence of the event. The atoms are then read out of the list and instructions corresponding to the atoms are generated and simulated to handle the event.

US Patent:

6625759, Sep 23, 2003

Filed:

Feb 18, 2000

Appl. No.:

09/502366

Inventors:

Jeremy Petsinger - Fort Collins CO
Kevin David Safford - Fort Collins CO
Karl P. Brummel - Fort Collins CO
Russell C. Brockmann - Fort Collins CO
Bruce A. Long - Loveland CO
Patrick Knebel - Ft Collins CO

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

H02H 305

US Classification:

714 28, 714 30, 714 34, 714 21

Abstract:

A method and an apparatus checks the fine-grain correctness of a microcode machine central processor unit (CPU) behavioral model. Macroinstructions are decomposed into microinstructions and each microinstruction is executed sequentially. A sequence of microinstructions is determined by an emulated microinstruction sequencer, using dynamic execution information, including information from execution of prior microinstructions in the sequence of microinstructions. At the end of execution of each microinstruction, a reference state is compared to a corresponding state of the behavioral model, and any differences are noted. After execution of all microinstructions in the microinstruction sequence, a reference state is compared to a corresponding state of the behavioral model, and any differences are noted.

US Patent:

6643800, Nov 4, 2003

Filed:

Feb 2, 2000

Appl. No.:

09/496367

Inventors:

Kevin David Safford - Fort Collins CO
Patrick Knebel - Ft Collins CO
Russell C Brockmann - Ft Collins CO
Karl P Brummel - Ft Collins CO

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1100

US Classification:

714 35, 712227

Abstract:

An apparatus and a method of testing computer microarchitectures has a test writer create a test sequence written directly in microinstructions (both native-mode and emulation-only microinstructions). The microinstruction sequence is then inserted into a reprogrammable microcode storage, replacing the normal sequence of microinstructions for a given macroinstruction. In order to execute the microinstructions, the test writer can issue the macroinstruction. The method may be implemented in a simulation model where one set of microinstructions in the reprogrammable microcode storage can be easily replaced. The method may also be applied to an actual microprocessor implementation.

US Patent:

6678853, Jan 13, 2004

Filed:

Dec 17, 1999

Appl. No.:

09/466503

Inventors:

Karl P Brummel - Ft Collins CO

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G01R 3128

US Classification:

714739, 714738

Abstract:

A method and apparatus produce random computer code for testing integrated circuit. The method begins by generating a random weight for an instruction type, and then generating randomly determined computer code. A statistical likelihood of generating the instruction type in the code is based on the random weight for the generated instruction type. The apparatus includes a random value generator that generates a random weight and a random code generator that is connected to the random value generator. The random code generator produces an output file in which the proportion of at least one computer instruction type is related to the random weight produced by the random value generator.

US Patent:

7139936, Nov 21, 2006

Filed:

Aug 22, 2003

Appl. No.:

10/645567

Inventors:

Jeremy Petsinger - Fort Collins CO, US
Kevin David Safford - Fort Collins CO, US
Karl P. Brummel - Fort Collins CO, US
Russell C. Brockmann - Fort Collins CO, US
Bruce A. Long - Loveland CO, US
Patrick Knebel - Ft Collins CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 11/00

US Classification:

714 28, 714 34, 703 14

Abstract:

An apparatus verifies the correctness of a behavioral model of a microcode machine, where the microcode machine is operable in a native state and an emulated state. The apparatus includes means for producing the native state, means for producing the emulated state, and means for comparing the native state and the emulated state. Corresponding to the apparatus, a method verifies the correctness of a processor behavioral model, where the processor operates in a native mode state and an emulated mode state. The method includes determining if a macroinstruction to be executed is a native instruction, and, if the macroinstruction is a native instruction, executing the native instruction, the execution producing the native mode state of the processor. The method further includes, if the macroinstruction is not a native instruction, fetching the macroinstruction, providing microinstructions corresponding to the macroinstruction, and executing the microinstructions, the execution producing the native mode state of the processor. Finally, the method includes executing the macroinstruction, the execution producing an emulated state of the processor, and comparing the native mode state the of the processor with the emulated state of the processor.

US Patent:

7152192, Dec 19, 2006

Filed:

Jan 20, 2005

Appl. No.:

11/039666

Inventors:

Karl P. Brummel - Chicago IL, US
Todd Mellinger - Fort Collins CO, US
J. Michael Hill - Fort Collins CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G11C 29/00
G11C 7/00
G06F 11/00

US Classification:

714718, 714820, 714710, 365201

Abstract:

A method of testing a plurality of memory blocks of an integrated circuit in parallel, wherein each memory block comprising data bit storage cells in an array of rows and columns, and wherein each row of storage cells is addressable to store a word of data bits having a width determined by the number of columns of the array, comprises the steps of: writing test data words in parallel to the rows of the plurality of memory blocks; reading out test data words in parallel from the rows of the plurality of memory blocks to a corresponding plurality of on-chip data word comparators; presenting corresponding expected data words in parallel to the plurality of on-chip data word comparators for comparison with the read out data words of the corresponding memory blocks; concurrently comparing corresponding data bits of the read out data words and expected data words in corresponding data bit comparators to generate a column status bit for each data bit comparison; latching the column status bit of a mismatch bit comparison in the corresponding data word comparator; and reading the column status bits of each on-chip data word comparator.

US Patent:

7409524, Aug 5, 2008

Filed:

Aug 17, 2005

Appl. No.:

11/205622

Inventors:

Kevin Safford - Fort Collins CO, US
Rohit Bhatia - Fort Collins CO, US
Karl Brummel - Chicago IL, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 12/00

US Classification:

711205, 711122, 711203, 711207

Abstract:

The present invention relates to an improved microprocessor having a memory system with several caches that can be operated to provide virtual memory. Among the caches included in the microprocessor are conventional caches that store data and instructions to be utilized by the processes being performed by the microprocessor, and that are typically arranged in a cache hierarchy, as well as one or more translation lookaside buffer (TLB) caches that store a limited number of virtual page translations. The improved microprocessor also has an additional cache that serves to store a virtual hash page table (VHPT) that is accessed when TLB misses occur. The introduction of this VHPT cache eliminates or at least reduces the need for the microprocessor to look for information within the caches of the cache hierarchy or in other memory (e. g. , main memory) outside of the microprocessor when TLB misses occur, and consequently enhances microprocessor speed.

US Patent:

7543113, Jun 2, 2009

Filed:

Jul 2, 2004

Appl. No.:

10/883860

Inventors:

Shawn Walker - Fort Collins CO, US
Karl Brummel - Chicago IL, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 12/00
G06F 13/00
G06F 13/28

US Classification:

711128, 711173

Abstract:

A cache memory system capable of adaptively accommodating various memory line sizes comprises cache memory and cache logic. The cache memory has sets of ways. The cache logic is configured to request a memory line in response to a cache miss, and the memory line represents a portion of a way line. The cache logic is configured to select one of the ways based on which portion of the way line is represented by the memory line. The cache logic is further configured to store the memory line in the selected way.