Lakshminarayan Krishnamurty

US Patent:

20030058014, Mar 27, 2003

Filed:

Sep 25, 2001

Appl. No.:

09/960998

Inventors:

Lakshminarayan Krishnamurty - Tempe AZ, US

International Classification:

H03L007/06

US Classification:

327/158000

Abstract:

A delay locked loop having short acquisition time to lock. The voltage controlled delay line includes a series of stages with the delay of each stage being variable. However, the initial stage has a fixed delay to avoid latching of the final stage to the first stage of the next cycle. The phase detector has additional logic gating to suppress an extraneous up or down signal during the acquisition time.