Lawrence L Liu

US Patent:

59497220, Sep 7, 1999

Filed:

Apr 16, 1998

Appl. No.:

9/062175

Inventors:

Lawrence Liu - Menlo Park CA
Li-Chun Li - Los Gatos CA
Michael Murray - Bellevue WA

Assignee:

Mosel Vitelic - San Jose CA

International Classification:

G11C 700

US Classification:

36518911

Abstract:

An input/output bias circuit used in MOS memory devices is insensitive to inadvertent power supply variations. A memory cell, programmed to a given state, has a terminal connected to a first node. A first MOS switch, normally open, is connected between the first node and a ground terminal. A biasing circuit and a second MOS switch, normally closed, are connected between a power supply terminal and the first node. The first node is connected to one of two input terminals of a sense amplifier, the second input terminal being connected to a sense amplifier enable/disable signal. Upon selecting the memory cell, the first switch is turned on and the second switch is turned off for a first period of time. During this period, the biasing circuit and the first switch interact to bias the first node to a potential equal to one threshold voltage below the supply voltage. During a second period of time immediately after the first period, both switches 1 and 2 are turned off.

US Patent:

58386220, Nov 17, 1998

Filed:

Feb 28, 1997

Appl. No.:

8/850933

Inventors:

Lawrence C. Liu - Menlo Park CA
Li-Chun Li - Los Gatos CA
Michael A. Murray - Bellevue WA

Assignee:

Mosel Vitelic Corporation - San Jose CA

International Classification:

G11C 800

US Classification:

36523002

Abstract:

A long X bit or a long Y bit is stored in a latch and used to supplement the Y address bits in an asymmetric DRAM memory thereby to allow one part to be used for a design requiring a long X bit and also for a design requiring a long Y bit.

US Patent:

58124748, Sep 22, 1998

Filed:

Oct 18, 1996

Appl. No.:

8/733858

Inventors:

Lawrence Liu - Menlo Park CA
Li-Chun Li - Los Gatos CA
Michael Murray - Bellevue WA

Assignee:

Mosel Vitelic Corporation - San Jose CA

International Classification:

G11C 702

US Classification:

365207

Abstract:

An input/output bias circuit used in MOS memory devices is insensitive to inadvertent power supply variations. A memory cell, programmed to a given state, has a terminal connected to a first node. A first MOS switch, normally open, is connected between the first node and a ground terminal. A biasing circuit and a second MOS switch, normally closed, are connected between a power supply terminal and the first node. The first node is connected to one of two input terminals of a sense amplifier, the second input terminal being connected to a sense amplifier enable/disable signal. Upon selecting the memory cell, the first switch is turned on and the second switch is turned off for a first period of time. During this period, the biasing circuit and the first switch interact to bias the first node to a potential equal to one threshold voltage below the supply voltage. During a second period of time immediately after the first period, both switches 1 and 2 are turned off.

US Patent:

57677379, Jun 16, 1998

Filed:

Aug 9, 1996

Appl. No.:

8/695058

Inventors:

Lawrence Liu - San Jose CA
Michael Murray - Bellevue WA
Li-Chun Li - Los Gatos CA

Assignee:

Mosel Vitelic - San Jose CA

International Classification:

G05F 110
G11C 706

US Classification:

327544

Abstract:

A dynamic random access memory generates an internal power supply voltage IVCC. IVCC is lower in magnitude than the external power supply voltage EVCC. During a read operation, the sense amplifiers are powered from EVCC while the bit lines charge to their output levels. Then the sense amplifiers stop being powered from EVCC and begin being powered from IVCC to maintain the bit lines at their output levels. A timer defines the time that the sense amplifiers are powered from EVCC. This time depends inversely on EVCC. The timer includes a transistor connected between EVCC and an input of the inverter. The time that the sense amplifiers are powered from EVCC is defined by the time that the input of the inverter charges to the trip point of the inverter.

US Patent:

60117370, Jan 4, 2000

Filed:

Nov 11, 1997

Appl. No.:

8/967436

Inventors:

Li-Chun Li - Los Gatos CA
Lawrence C. Liu - Menlo Park CA
Michael A. Murray - Bellevue WA

Assignee:

Mosel Vitelic Corporation - San Jose CA

International Classification:

G11C 700

US Classification:

365207

Abstract:

A staggered bitline sense amplifier architecture utilizes a circuit to simulate the effect of a memory cell on each of the edge sense amplifiers not selected for connection to an activated memory cell, thereby to allow the edge sense amplifiers to be activated simultaneously with the sense amplifiers internal to the memory array without the danger of burning out the edge sense amplifiers. This structure eliminates the address decoding circuitry commonly associated with the edge sense amplifiers used in staggered shared bitline sense amplifier architectures, thereby decreasing the complexity and reducing the chip size of such memory arrays.

US Patent:

57682003, Jun 16, 1998

Filed:

Dec 3, 1996

Appl. No.:

8/760121

Inventors:

Lawrence Liu - Menlo Park CA
Michael Murray - Bellevue WA
Li-Chun Li - Los Gatos CA

Assignee:

Mosel Vitelic Corporation - San Jose CA

International Classification:

G11C 700

US Classification:

365203

Abstract:

A sense amplifier charging circuit can work with different power supply voltages (EVCC). When EVCC is high, a signal generated from EVCC disables some of the charging transistors to reduce the circuit noise. When EVCC is low, the signal generated from EVCC enables the transistors thus increasing the circuit speed.

US Patent:

59663383, Oct 12, 1999

Filed:

Mar 24, 1998

Appl. No.:

9/047304

Inventors:

Lawrence C. Liu - Menlo Park CA
Michael A. Murray - Bellevue WA
Li-Chun Li - Los Gatos CA

Assignee:

Mosel Vitelic Corporation - San Jose CA

International Classification:

G11C 702

US Classification:

365207

Abstract:

In accordance with this invention, a DRAM with a staggered bitline sense amplifier configuration utilizes an I/O data path scheme which minimizes the time delay through the I/O data path. The DRAM includes a first and a second memory arrays wherein a first external sense amplifier receives on an input terminal a signal corresponding to the state of a memory cell selected from the first memory array via a first column decoding circuit. A second external sense amplifier receives on an input terminal a signal corresponding to the state of a memory cell selected form the second memory array via a second column decoding circuit. Each of the two external sense amplifiers has an output terminal which are shorted together. A tristate signal feeding another input terminal of each of the two external sense amplifiers is used to eliminate data contention on the shorted output terminals.

US Patent:

57577102, May 26, 1998

Filed:

Dec 3, 1996

Appl. No.:

8/760124

Inventors:

Li-Chun Li - Los Gatos CA
Lawrence C. Liu - Menlo Park CA
Michael A. Murray - Bellevue WA

Assignee:

Mosel Vitelic Corporation - San Jose CA

International Classification:

G11C 700

US Classification:

365205

Abstract:

A staggered bitline sense amplifier architecture utilizes a circuit to simulate the effect of a memory cell on each of the edge sense amplifiers not selected for connection to an activated memory cell, thereby to allow the edge sense amplifiers to be activated simultaneously with the sense amplifiers internal to the memory array without the danger of burning out the edge sense amplifiers. This structure eliminates the address decoding circuitry commonly associated with the edge sense amplifiers used in staggered shared bitline sense amplifier architectures, thereby decreasing the complexity and reducing the chip size of such memory arrays.