Liren Liu Liu

US Patent:

7831856, Nov 9, 2010

Filed:

Apr 3, 2008

Appl. No.:

12/061885

Inventors:

Liren Liu - Sunnyvale CA, US
Jianshe He - Cupertino CA, US
Shangzhi Sun - San Jose CA, US

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

G06F 11/00

US Classification:

714 2, 714700

Abstract:

In one example, a method of detecting timing errors in a configuration of a programmable logic device (PLD) includes performing a timing analysis on the PLD configuration. The PLD configuration is adapted to configure the PLD to perform a data transfer between a first clock domain synchronized by a first clock signal received by a double data rate (DDR) block of the PLD configuration and a second clock domain synchronized by a second clock signal received by the DDR block. The method includes calculating a slack value associated with the data transfer using a first delay associated with the first clock signal, a second delay associated with the second clock signal, and a time constraint associated with the data transfer. The first delay and the second delay are provided by the timing analysis. The method includes determining whether the PLD configuration satisfies the time constraint based on the slack value.

US Patent:

20040088663, May 6, 2004

Filed:

Nov 5, 2002

Appl. No.:

10/288668

Inventors:

Qinghong Wu - Santa Clara CA, US
Yinan Shen - Sunnyvale CA, US
Liren Liu - Sunnyvale CA, US

International Classification:

G06F017/50

US Classification:

716/006000

Abstract:

A method for placing configurable logic blocks (CLBs) in a PLD, such as an FPGA. In one embodiment, after packing gates/clusters into blocks and then assigning those blocks to CLBs to generate an initial placement, the packing and/or placement of CLBs is changed prior to performing CLB routing. For each node of the most critical of the K most critical paths in the initial placement, moving the node to a different CLB is considered in order to reduce the criticality of that path. A move is applied if certain acceptability conditions are met. After the most critical path is improved, the criticality of the K paths is updated, and the procedure is repeated for the new most critical of the K updated paths. The method, which can be automated to reduce human intervention in the design process, improves circuit performance, e.g., by enabling higher circuit operation frequencies.