Loc L Tu from San Jose, CA, age 50

Resumes

Business Taxes Specialist

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Location:

6240 Sun River Dr, Sacramento, CA 95824

Industry:

Government Administration

Work:

California Department of Tax and Fee Administration
Business Taxes Specialist
California Department of Tax and Fee Administration Sep 2016 - Oct 2019
Senior Tax Auditor
California State Board of Equalization May 2013 - Aug 2016
Tax Auditor
Lincare Holdings, Inc Sep 2009 - Jun 2011
Sales Representative
Wells Fargo Dec 2006 - Dec 2007
Consumer Loan Underwriter

Education:

Los Rios Community College 2011 - 2013
Associates, Associate of Arts, Accounting University of California, Davis 1995 - 2000
Bachelors, Bachelor of Arts, Economics

Skills:

Financial Services
Financial Analysis
Portfolio Management
Investments
Securities
Credit
Series 7
Finance
Sales
Loans

Senior Director, Engineering Fellow

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Location:

San Francisco, CA

Industry:

Semiconductors

Work:

Sandisk
Senior Director, Engineering Fellow

Skills:

Semiconductors
Engineering

Us Patents

Error Recovery For Nonvolatile Memory
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US Patent:

7099194, Aug 29, 2006
Filed:

Dec 3, 2004
Appl. No.:

11/003545
Inventors:

Loc Tu - San Jose CA, US
Jian Chen - San Jose CA, US
Assignee:

SanDisk Corporation - Milpitas CA
International Classification:

G11C 16/04
US Classification:

36518518, 36518521, 36518529
Abstract:

An error recovery technique is used on marginal nonvolatile memory cells. A marginal memory cell is unreadable because it has a voltage threshold (VT) of less than zero volts. By biasing adjacent memory cells, this will shift the voltage threshold of the marginal memory cells, so that it is a positive value. Then the VT of the marginal memory cell can be determined. The technique is applicable to both binary and multistate memory cells.

Flash Memory Devices With Trimmed Analog Voltages
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US Patent:

7254071, Aug 7, 2007
Filed:

Jan 12, 2006
Appl. No.:

11/332567
Inventors:

Loc Tu - San Jose CA, US
Jeffrey Lutze - San Jose CA, US
Jun Wan - Sunnyvale CA, US
Jian Chen - Sunnyvale CA, US
Assignee:

SanDisk Corporation - Milpitas CA
International Classification:

G11C 29/00
US Classification:

365201, 36518518, 36518521
Abstract:

A flash memory device of the multi-level cell (MLC) type, in which control gate voltages in read and programming operations and a bandgap reference voltage source are trimmable from external terminals, is disclosed. In a special test mode, control gate voltages can be applied to a selected programmed memory cell so that the threshold voltage of the cell can be sensed. A digital-to-analog converter (DAC) use for programming and a second read/verify DAC apply varying analog voltages and are sequentially used to verify the programming of an associated set of memory cells in this special test mode, with the DAC input values that provide the closest result selected for use in normal operation. These DAC's are dependent on the value of a reference source that my also be trimmed.

Method For Non-Volatile Memory With Linear Estimation Of Initial Programming Voltage
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US Patent:

7453731, Nov 18, 2008
Filed:

Sep 12, 2006
Appl. No.:

11/531227
Inventors:

Loc Tu - San Jose CA, US
Charles Moana Hook - Patterson CA, US
Yan Li - Milipitas CA, US
Assignee:

Sandisk Corporation - Milpitas CA
International Classification:

G11C 16/04
US Classification:

36518518, 36518522, 3651852, 36518511, 36523003, 3652385, 365235, 36518529, 36518519, 714 30
Abstract:

In a non-volatile memory, a selected page on a word line is successively programmed by a series of voltage pulses of a staircase waveform with verifications in between the pulses until the page is verified to a designated pattern. The programming voltage at the time the page is programmed verified will be to estimate the initial value of a starting programming voltage for the page. The estimation is further refined by using the estimate from a first pass in a second pass. Also, when the test is over multiple blocks, sampling of word lines based on similar geometrical locations of the blocks can yield a starting programming voltage optimized for faster programming pages.

Trimming Of Analog Voltages In Flash Memory Devices
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US Patent:

7457178, Nov 25, 2008
Filed:

Jan 12, 2006
Appl. No.:

11/331479
Inventors:

Loc Tu - San Jose CA, US
Jeffrey Lutze - San Jose CA, US
Jun Wan - Sunnyvale CA, US
Jian Chen - Sunnyvale CA, US
Assignee:

SanDisk Corporation - Milpitas CA
International Classification:

G11C 29/00
US Classification:

365201, 36518518, 36518524
Abstract:

A flash memory device of the multi-level cell (MLC) type, in which control gate voltages in read and programming operations and a bandgap reference voltage source are trimmable from external terminals, is disclosed. In a special test mode, control gate voltages can be applied to a selected programmed memory cell so that the threshold voltage of the cell can be sensed. A digital-to-analog converter (DAC) use for programming and a second read/verify DAC apply varying analog voltages and are sequentially used to verify the programming of an associated set of memory cells in this special test mode, with the DAC input values that provide the closest result selected for use in normal operation. These DAC's are dependent on the value of a reference source that my also be trimmed.

Systems For Programmable Chip Enable And Chip Address In Semiconductor Memory
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US Patent:

7477545, Jan 13, 2009
Filed:

Jun 14, 2007
Appl. No.:

11/763292
Inventors:

Loc Tu - San Jose CA, US
Jian Chen - San Jose CA, US
Alex Mak - Los Altos Hills CA, US
Tien-Chien Kuo - Sunnyvale CA, US
Long Pham - San Ramon CA, US
Assignee:

SanDisk Corporation - Milpitas CA
International Classification:

G11C 16/04
US Classification:

36518505, 365 52, 365 63
Abstract:

Memory die are provided with programmable chip enable circuitry to allow particular memory die to be disabled after packaging and/or programmable chip address circuitry to allow particular memory die to be readdressed after being packaged. In a multi-chip memory package, a memory die that fails package-level testing can be disabled and isolated from the memory package by a programmable circuit that overrides the master chip enable signal received from the controller or host device. To provide a continuous address range, one or more of the non-defective memory die can be re-addressed using another programmable circuit that replaces the unique chip address provided by the pad bonding. Memory chips can also be also be readdressed after packaging independently of detecting a failed memory die.

Defective Block Isolation In A Non-Volatile Memory System
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US Patent:

7561482, Jul 14, 2009
Filed:

Sep 7, 2006
Appl. No.:

11/470945
Inventors:

Loc Tu - San Jose CA, US
Wangang Tsai - Sunnyvale CA, US
Assignee:

Sandisk Corporation - Milpitas CA
International Classification:

G11C 29/00
G11C 7/00
US Classification:

365200, 365201
Abstract:

A method and apparatus provide an improved identification and isolation of defective blocks in non-volatile memory devices having a plurality of user accessible blocks of non-volatile storage elements where each block also has an associated defective block latch. The method provides for sensing each defective block latch to determine whether the defective block latch was set due to a defect, and storing, in temporary on chip memory, address data corresponding to each set latch. The method further involves retrieving the address data and disabling defective blocks based upon the address data. A non-volatile memory device is also described having a controller which senses the defective block latches, stores address data for each block having a set latch, and subsequently retrieves the stored address data to set the defective block latches based upon the address data.

Non-Volatile Memory With Linear Estimation Of Initial Programming Voltage
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US Patent:

7599223, Oct 6, 2009
Filed:

Sep 12, 2006
Appl. No.:

11/531230
Inventors:

Loc Tu - San Jose CA, US
Charles Moana Hook - Patterson CA, US
Yan Li - Milipitas CA, US
Assignee:

SanDisk Corporation - Milpitas CA
International Classification:

G11C 16/06
US Classification:

36518522, 36518518, 36518524, 36518529, 36518526, 36518533
Abstract:

In a non-volatile memory, a selected page on a word line is successively programmed by a series of voltage pulses of a staircase waveform with verifications in between the pulses until the page is verified to a designated pattern. The programming voltage at the time the page is programmed verified will be to estimate the initial value of a starting programming voltage for the page. The estimation is further refined by using the estimate from a first pass in a second pass. Also, when the test is over multiple blocks, sampling of word lines based on similar geometrical locations of the blocks can yield a starting programming voltage optimized for faster programming pages.

Non-Volatile Memory With Reduced Erase/Write Cycling During Trimming Of Initial Programming Voltage
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US Patent:

7606077, Oct 20, 2009
Filed:

Sep 12, 2006
Appl. No.:

11/531223
Inventors:

Yan Li - Milpitas CA, US
Loc Tu - San Jose CA, US
Charles Moana Hook - Patterson CA, US
Assignee:

SanDisk Corporation - Milpitas CA
International Classification:

G11C 16/06
US Classification:

36518522, 36518529, 365201
Abstract:

High performance non-volatile memory devices have the programming voltages trimmed for individual types of memory pages and word lines. A group of word lines within each erasable block of memory are tested successive program loops to minimize the problem of incurring excessive number of erase/program cycles. An optimum programming voltage for a given type of memory pages is derived from statistical results of a sample of similar of memory pages.