Mandeep Singh

US Patent:

20170337063, Nov 23, 2017

Filed:

Aug 9, 2017

Appl. No.:

15/673286

Inventors:

- Santa Clara CA, US
Mandeep Singh - Union City CA, US

International Classification:

G06F 9/38

Abstract:

A method for sorting elements in hardware structures is disclosed. The method comprises selecting a plurality of elements to order from an unordered input queue (UIQ) within a predetermined range in response to finding a match between at least one most significant bit of the predetermined range and corresponding bits of a respective identifier associated with each of the plurality of elements. The method further comprises presenting each of the plurality of elements to a respective multiplexer. Further the method comprises generating a select signal for an enabled multiplexer in response to finding a match between at least one least significant bit of a respective identifier associated with each of the plurality of elements and a port number of the ordered queue. Finally, the method comprises forwarding a packet associated with a selected element identifier to a matching port number of the ordered queue from the enabled multiplexer.

US Patent:

20150248294, Sep 3, 2015

Filed:

Oct 21, 2011

Appl. No.:

14/376825

Inventors:

Mandeep Singh - Union City CA, US
Mohammad Abdallah - San Jose CA, US

Assignee:

SOFT MACHINES, INC - Santa Clara CA

International Classification:

G06F 9/30
G06F 12/08
G06F 13/16

Abstract:

Fast unaligned memory access. In accordance with a first embodiment of the present invention, a computing device includes a load queue memory structure configured to queue load operations and a store queue memory structure configured to queue store operations. The computing device includes also includes at least one bit configured to indicate the presence of an unaligned address component for an entry of said load queue memory structure, and at least one bit configured to indicate the presence of an unaligned address component for an entry of said store queue memory structure. The load queue memory may also include memory configured to indicate data forwarding of an unaligned address component from said store queue memory structure to said load queue memory structure.