Mandeep Singh

US Patent:

20110296264, Dec 1, 2011

Filed:

May 27, 2010

Appl. No.:

12/788983

Inventors:

Amit Chandra - Milpitas CA, US
Mandeep Singh - San Jose CA, US
Michael Mar - Cupertino CA, US

International Classification:

G01R 31/3177
G06F 11/25

US Classification:

714729, 714E11155

Abstract:

In an embodiment, a design methodology and tools to implement the methodology are used to perform scan insertion in an integrated circuit design. The physical location of the scan chains within the boundaries of the integrated circuit may be determined, and the methodology may use the physical information to perform the scan insertion. For example, the physical information may include the location of the inputs and outputs of the scan chains, as well as routability data indicating the ability to insert interconnect in the integrated circuit to make the desired scan connections. The location and routability information may be used to group scan chain inputs and outputs for, e.g., compression/decompression logic. Using physical data to insert scan compression/decompression logic may reduce the amount of area occupied by the scan logic and connectivity, in some embodiments.

US Patent:

20190056964, Feb 21, 2019

Filed:

Oct 19, 2018

Appl. No.:

16/166010

Inventors:

- Santa Clara CA, US
Ankur Groen - Santa Clara CA, US
Erika Gunadi - Los Gatos CA, US
Mandeep Singh - Union City CA, US
Ravishankar Rao - Redwood City CA, US

International Classification:

G06F 9/455
G06F 12/109
G06F 12/1036
G06F 12/1027
G06F 12/0875
G06F 9/30
G06F 9/38
G06F 9/32

Abstract:

Methods for supporting wide and efficient front-end operation with guest architecture emulation are disclosed. As a part of a method for supporting wide and efficient front-end operation, upon receiving a request to fetch a first far taken branch instruction, a cache line that includes the first far taken branch instruction, a next cache line and a cache line located at the target of the first far taken branch instruction is read. Based on information that is accessed from a data table, the cache line and either the next cache line or the cache line located at the target is fetched in a single cycle.

US Patent:

20170337063, Nov 23, 2017

Filed:

Aug 9, 2017

Appl. No.:

15/673286

Inventors:

- Santa Clara CA, US
Mandeep Singh - Union City CA, US

International Classification:

G06F 9/38

Abstract:

A method for sorting elements in hardware structures is disclosed. The method comprises selecting a plurality of elements to order from an unordered input queue (UIQ) within a predetermined range in response to finding a match between at least one most significant bit of the predetermined range and corresponding bits of a respective identifier associated with each of the plurality of elements. The method further comprises presenting each of the plurality of elements to a respective multiplexer. Further the method comprises generating a select signal for an enabled multiplexer in response to finding a match between at least one least significant bit of a respective identifier associated with each of the plurality of elements and a port number of the ordered queue. Finally, the method comprises forwarding a packet associated with a selected element identifier to a matching port number of the ordered queue from the enabled multiplexer.

US Patent:

20160328238, Nov 10, 2016

Filed:

Jul 20, 2016

Appl. No.:

15/215004

Inventors:

- Santa Clara CA, US
Mandeep SINGH - Newark CA, US

International Classification:

G06F 9/38

Abstract:

A method for sorting elements in hardware structures is disclosed. The method comprises selecting a plurality of elements to order from an unordered input queue (UIQ) within a predetermined range in response to finding a match between at least one most significant bit of the predetermined range and corresponding bits of a respective identifier associated with each of the plurality of elements. The method further comprises presenting each of the plurality of elements to a respective multiplexer. Further the method comprises generating a select signal for an enabled multiplexer in response to finding a match between at least one least significant bit of a respective identifier associated with each of the plurality of elements and a port number of the ordered queue. Finally, the method comprises forwarding a packet associated with a selected element identifier to a matching port number of the ordered queue from the enabled multiplexer.

US Patent:

20150248294, Sep 3, 2015

Filed:

Oct 21, 2011

Appl. No.:

14/376825

Inventors:

Mandeep Singh - Union City CA, US
Mohammad Abdallah - San Jose CA, US

Assignee:

SOFT MACHINES, INC - Santa Clara CA

International Classification:

G06F 9/30
G06F 12/08
G06F 13/16

Abstract:

Fast unaligned memory access. In accordance with a first embodiment of the present invention, a computing device includes a load queue memory structure configured to queue load operations and a store queue memory structure configured to queue store operations. The computing device includes also includes at least one bit configured to indicate the presence of an unaligned address component for an entry of said load queue memory structure, and at least one bit configured to indicate the presence of an unaligned address component for an entry of said store queue memory structure. The load queue memory may also include memory configured to indicate data forwarding of an unaligned address component from said store queue memory structure to said load queue memory structure.

US Patent:

20140281409, Sep 18, 2014

Filed:

Mar 13, 2014

Appl. No.:

14/209736

Inventors:

- Santa Clara CA, US
Mandeep SINGH - Newark CA, US

Assignee:

Soft Machines, Inc. - Santa Clara CA

International Classification:

G06F 9/38

US Classification:

712216

Abstract:

A method for performing memory disambiguation in an out-of-order microprocessor pipeline is disclosed. The method comprises storing a tag with a load operation, wherein the tag is an identification number representing a store instruction nearest to the load operation, wherein the store instruction is older with respect to the load operation and wherein the store has potential to result in a RAW violation in conjunction with the load operation. The method also comprises issuing the load operation from an instruction scheduling module. Further, the method comprises acquiring data for the load operation speculatively after the load operation has arrived at a load store queue module. Finally, the method comprises determining if an identification number associated with a last contiguous issued store with respect to the load operation is equal to or greater than the tag and gating a validation process for the load operation in response to the determination.

US Patent:

20140281422, Sep 18, 2014

Filed:

Oct 11, 2013

Appl. No.:

14/052571

Inventors:

- Santa Clara CA, US
Mandeep SINGH - Newark CA, US

Assignee:

Soft Machines, Inc. - Santa Clara CA

International Classification:

G06F 9/30

US Classification:

712223

Abstract:

A method for sorting elements in hardware structures is disclosed. The method comprises selecting a plurality of elements to order from an unordered input queue (UIQ) within a predetermined range in response to finding a match between at least one most significant bit of the predetermined range and corresponding bits of a respective identifier associated with each of the plurality of elements. The method further comprises presenting each of the plurality of elements to a respective multiplexer. Further the method comprises generating a select signal for an enabled multiplexer in response to finding a match between at least one least significant bit of a respective identifier associated with each of the plurality of elements and a port number of the ordered queue. Finally, the method comprises forwarding a packet associated with a selected element identifier to a matching port number of the ordered queue from the enabled multiplexer.

US Patent:

20140282546, Sep 18, 2014

Filed:

Mar 17, 2014

Appl. No.:

14/216493

Inventors:

- Santa Clara CA, US
Ankur Groen - Santa Clara CA, US
Erika Gunadi - Los Gatos CA, US
Mandeep Singh - Newark CA, US
Ravishankar Rao - Foster City CA, US

Assignee:

Soft Machines, Inc. - Santa Clara CA

International Classification:

G06F 9/455
G06F 12/10
G06F 9/30
G06F 12/08

US Classification:

718 1, 711125

Abstract:

Methods for supporting wide and efficient front-end operation with guest architecture emulation are disclosed. As a part of a method for supporting wide and efficient front-end operation, upon receiving a request to fetch a first far taken branch instruction, a cache line that includes the first far taken branch instruction, a next cache line and a cache line located at the target of the first far taken branch instruction is read. Based on information that is accessed from a data table, the cache line and either the next cache line or the cache line located at the target is fetched in a single cycle.