Mark R Hilbert

US Patent:

6377504, Apr 23, 2002

Filed:

Dec 12, 2000

Appl. No.:

09/735336

Inventors:

Mark Francis Hilbert - Naperville IL

Assignee:

Tachuon Semiconductor Corp - Naperville IL

International Classification:

G11C 800

US Classification:

36523003, 36518902, 36523002, 365207, 36523006

Abstract:

A memory that includes a plurality of storage blocks. Each block has a plurality of storage cells constructed from a storage element and an isolation transistor. The storage cells in a block are organized as a plurality of rows and column units. Each column unit includes a first bit line and a plurality of the memory cells connected to the first bit line by the isolation transistors in those memory cells. The memory also includes a first multiplexer connected to a plurality of the first bit lines in a first one of the memory blocks, the first multiplexer connecting one of the first bit lines to a first conductor in response to one or more first multiplexer control signals. The first multiplexer is located adjacent to the storage block containing first bit lines connected thereto. The first conductor is connected to a sense amplifier for reading the contents of the storage cells. The sense amplifier may be located adjacent to the first multiplexer or at a remote location relative to the storage block.

US Patent:

6469945, Oct 22, 2002

Filed:

May 18, 2001

Appl. No.:

09/861076

Inventors:

Robert Patti - Warrenville IL
Mark Francis Hilbert - Naperville IL

Assignee:

Tachyon Semiconductor Corp. - San Jose CA

International Classification:

G11C 700

US Classification:

365201, 365200, 365 49

Abstract:

A reconfigurable memory having M bit lines and a plurality of row lines, where M 1. The memory includes an array of memory storage cells, each memory storage cell storing a data value. The data value is read from or into the storage cells by coupling that data value to one of the bit lines in response to a row control signal on one of the row lines. A row select circuit generates the row control signal on one of the row lines in response to a row address being coupled to the row select circuit. The row select circuit includes a memory for storing a mapping of the row addresses to the row lines that determines which of the row lines is selected for each possible value of the row address.

US Patent:

6525987, Feb 25, 2003

Filed:

May 23, 2001

Appl. No.:

09/864493

Inventors:

Mark Francis Hilbert - Naperville IL

Assignee:

Tachyon Semiconductor Corporation - San Jose CA

International Classification:

G11C 800

US Classification:

36523006, 365200, 36523002

Abstract:

A memory having a two-dimensional array of memory cells organized as a plurality of rows and columns. The memory includes spare rows and columns. A controller in the memory tests the memory at power up and determines if any of the rows or columns are defective. A defective row or column is re-mapped to one of the spare rows or columns, respectively. Data specifying the re-mapping is stored in a separate re-mapping address decode circuit. When an address specifying a memory cell is received by the memory, a conventional address decode circuit decodes the address at the same time the re-mapping decoder searches for a match to the address. If the re-mapping decoder finds the address, it inhibits the conventional decoder and supplies the appropriate column or row select signals. The re-mapping decoder is preferably constructed from a content-addressable memory.

US Patent:

20030046630, Mar 6, 2003

Filed:

Sep 5, 2001

Appl. No.:

09/947320

Inventors:

Mark Hilbert - Warrenville IL, US

International Classification:

G11C029/00
G06F013/00

US Classification:

714/763000, 711/105000

Abstract:

A memory that corrects storage errors during those periods in which the memory is not servicing read/write instructions from an external system. The memory reads and writes data words that are stored in a storage block that includes a plurality of storage words. Each storage word stores a data entry specifying one of the data words. The data entry is encoded with error-correcting information sufficient to correct a one-bit error in the data word. The storage words are connected to the error-correcting circuit during idle periods or during the conventional refresh operations in the case of DRAM-like memories. The controller also causes each corrected storage word to be re-written to the storage block in place of the storage word from which the corrected storage word was generated if an error is detected by the error-correcting circuitry.

US Patent:

59830824, Nov 9, 1999

Filed:

Oct 31, 1997

Appl. No.:

8/962580

Inventors:

Mark Francis Hilbert - Naperville IL

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H04B 140

US Classification:

455 76

Abstract:

A variable phase shift network (420) for a phase quadrature signal generator (320, 370) includes a variable current controller (909), a first NPN transistor (801) and a second NPN transistor (802). The variable phase shift network (420) produces a first quadrature input signal (830), a second quadrature input signal (834), a first quadrature output signal (821) and a second quadrature output signal (826) responsive to receiving a first differential input signal (919) and a second differential input signal (925). The variable current controller (909) controls current in a first NPN transistor (801) to vary an emitter resistance (846) in the first NPN transistor (801) and controls current in a second NPN transistor (802) to vary an emitter resistance (847) in the second NPN transistor (802) to adjust a phase quadrature relationship between the first quadrature output signal (821) and the first quadrature input signal (830) and to adjust a phase quadrature relationship between the second quadrature output signal (826) and the second quadrature input signal (834).