Matthew Peter Wilson

US Patent:

52221970, Jun 22, 1993

Filed:

Jun 28, 1990

Appl. No.:

7/545072

Inventors:

Henry S. Teng - Groton MA
Kaihu Chen - Shirley MA
Matthew Wilson - Westville IL
Michael P. Verdeven - Westboro MA
Gregory B. Abbruzzese - Maynard MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 1518

US Classification:

395 68

Abstract:

A rule invocation mechanism in an inductive learning engine employing symbolic rules for characterizing a sequence of time-related events. The rules to be tested as hypotheses against new events in the sequence are ranked according to their information content or "quality" value. The efficiency of the rule-to-event pattern matching process for characterizing the new events is increased by not testing a hypothesis if a much better hypothesis already exists. Those hypotheses that characterize events in the sequence are tagged to the event.

US Patent:

20200055836, Feb 20, 2020

Filed:

Aug 16, 2019

Appl. No.:

16/542583

Inventors:

- Cambridge MA, US
Emily Patricia Balskus - Somerville MA, US
Matthew Ryan Wilson - Cambridge MA, US

Assignee:

PRESIDENT AND FELLOWS OF HARVARD COLLEGE - Cambridge MA

International Classification:

C07D 311/16
G01N 33/58

Abstract:

The technology described herein is directed to compounds which are substrates for ClbP, acting as fluorescent probes for ClbP activity. Further provided herein are methods for measuring ClbP activity, screening for ClbP inhibitors, detecting colibactin, and/or diagnosing cancer, which utilize the substrate compounds.

US Patent:

20170308696, Oct 26, 2017

Filed:

Jul 6, 2017

Appl. No.:

15/643408

Inventors:

- Seattle WA, US
Nachiketh Rao Potlapally - Arlington VA, US
William John Earl - Burien WA, US
Matthew Shawn Wilson - Seattle WA, US

International Classification:

G06F 21/55
G06F 9/50
G06F 9/46
G06F 21/53
G06F 9/455

Abstract:

Techniques are described for allocating resources to a task from a shared hardware structure. A plurality of tasks may execute on a processor, wherein the processor may include one or more processing cores and each task may include a plurality of computer executable instructions. In accordance with one technique for allocating resources to a task from a shared hardware structure amongst multiple tasks, aspects of the disclosure describe assigning a first identifier to a first task from the plurality of tasks, associating a portion of the shared hardware resource with the first identifier, and restricting access and/or observability for computer executable instructions executed from any other task than the first task to the portion of the hardware resource associated with the first identifier.

US Patent:

20160092677, Mar 31, 2016

Filed:

Sep 30, 2014

Appl. No.:

14/502891

Inventors:

- Seattle WA, US
Nachiketh Rao Potlapally - Arlington VA, US
William John Earl - Burien WA, US
Matthew Shawn Wilson - Seattle WA, US

International Classification:

G06F 21/55
G06F 9/50
G06F 9/455

Abstract:

Techniques are described for allocating resources to a task from a shared hardware structure. A plurality of tasks may execute on a processor, wherein the processor may include one or more processing cores and each task may include a plurality of computer executable instructions. In accordance with one technique for allocating resources to a task from a shared hardware structure amongst multiple tasks, aspects of the disclosure describe assigning a first identifier to a first task from the plurality of tasks, associating a portion of the shared hardware resource with the first identifier, and restricting access and/or observability for computer executable instructions executed from any other task than the first task to the portion of the hardware resource associated with the first identifier.