Michael V Le

US Patent:

7162002, Jan 9, 2007

Filed:

Oct 31, 2002

Appl. No.:

10/284341

Inventors:

Chun-Ying Chen - Irvine CA, US
Michael Q Le - Irvine CA, US
Myles Wakayama - Laguna Niguel CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03D 3/24

US Classification:

375376, 375362, 375373, 375374, 375375, 455260

Abstract:

A phase lock loop frequency synthesizer includes a phase rotator in the feedback path of the PLL. The PLL includes a phase detector, a low pass filter, a charge pump, a voltage controlled oscillator (“VCO”), and a feed back path connecting output of the VCO to the phase detector. The feedback path includes a phase rotator connected to the output of the VCO and to an input of a frequency divider. Coarse frequency control is implemented by adjusting the input reference frequency to the phase detector or by adjusting the divider ratio of the frequency divider. Fine frequency control is achieved by increasing or decreasing the rotation speed of the phase rotator. The phase rotator constantly rotates phase of the VCO output, thereby causing a frequency shift at the output of the phase rotator. The rotation speed of the phase rotator is controlled by an accumulator and a digital frequency control word. Any high frequency noise generated by the phase rotator is rejected by the PLL by properly setting the PLL bandwidth so that the noise falls outside the bandwidth of the PLL.

US Patent:

7486721, Feb 3, 2009

Filed:

Aug 21, 2007

Appl. No.:

11/892290

Inventors:

Kevin T. Chan - Pasadena CA, US
Michael Q. Le - Laguna Niguel CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H04B 1/38
H03M 9/00

US Classification:

375219, 375259, 341100, 341101

Abstract:

A physical layer device (PLD) includes a first serializer-deserializer (SERDES) device and a second SERDES device. Each SERDES device includes an analog portion with a serial port that is configured to communicate serial data with various network devices, and a digital portion that is configured to communicate parallel data with other various network devices. The PLD includes a first signal path that is configured to route serial data signals between the analog portions of the SERDES devices, bypassing the digital portions of the SERDES devices. Therefore, the SERDES devices can directly communicate serial data without performing parallel data conversion. A second signal path is configured to route recovered clock and data signals between the analog portions of the SERDES devices, but still bypassing the digital portions of the SERDES devices. The recovered clock and data signals are then regenerated before being transmitted over a network device.

US Patent:

7583772, Sep 1, 2009

Filed:

Oct 3, 2005

Appl. No.:

11/240678

Inventors:

Hui Pan - Irvine CA, US
Seong-Ho Lee - Aliso Viejo CA, US
Michael Q. Le - Laguna Niguel CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H04L 7/00

US Classification:

375372, 375371, 375259, 375354, 375355

Abstract:

A system and method are used to allow for phase rotator control signals to be produced that rotate bits in the signals more than one step per clock cycle. This can be done through the following operation. First and second data signals that include a plurality of data bits are stored. Rotation of data bits in the first data signal and subsequently data bits in the second data signal is controlled based on a phase control signal during each clock cycle. The first and second controlled data signals are interleaved to form first and second interleaved data signals. One of the first and second interleaved data signals is selected based on a portion of the phase control signal during a second half of the clock cycle. Finally, the selected data signal is transmitted as the phase control signal.

US Patent:

7706433, Apr 27, 2010

Filed:

Jan 15, 2009

Appl. No.:

12/320041

Inventors:

Kevin T. Chan - Pasadena CA, US
Michael Q. Le - Laguna Niguel CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H04B 1/38
H03M 9/00

US Classification:

375219, 375259, 341100, 341101

Abstract:

A physical layer device (PLD) includes a first serializer-deserializer (SERDES) device and a second SERDES device. Each SERDES device includes an analog portion with a serial port that is configured to communicate serial data with various network devices, and a digital portion that is configured to communicate parallel data with other various network devices. The PLD includes a first signal path that is configured to route serial data signals between the analog portions of the SERDES devices, bypassing the digital portions of the SERDES devices. Therefore, the SERDES devices can directly communicate serial data without performing parallel data conversion. A second signal path is configured to route recovered clock and data signals between the analog portions of the SERDES devices, but still bypassing the digital portions of the SERDES devices. The recovered clock and data signals are then regenerated before being transmitted over a network device.

US Patent:

8233578, Jul 31, 2012

Filed:

Jan 5, 2007

Appl. No.:

11/649809

Inventors:

Chun-Ying Chen - Irvine CA, US
Michael Q. Le - Irvine CA, US
Myles Wakayama - Laguna Niguel CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03D 3/24

US Classification:

375376, 375354, 375316, 327147, 327156, 342103

Abstract:

A phase lock loop frequency synthesizer includes a phase rotator in the feedback path of the PLL. The PLL includes a phase detector, a low pass filter, a charge pump, a voltage controlled oscillator (“VCO”), and a feedback path connecting output of the VCO to the phase detector. The feedback path includes a phase rotator connected to the output of the VCO and to an input of a frequency divider. Coarse frequency control is implemented by adjusting the input reference frequency to the phase detector or by adjusting the divider ratio of the frequency divider. Fine frequency control is achieved by increasing or decreasing the rotation speed of the phase rotator. The phase rotator constantly rotates phase of the VCO output, thereby causing a frequency shift at the output of the phase rotator.

US Patent:

8443124, May 14, 2013

Filed:

Mar 19, 2010

Appl. No.:

12/659739

Inventors:

Kevin T. Chan - Pasadena CA, US
Michael Q. Le - Laguna Niguel CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G06F 13/12
H04L 12/50

US Classification:

710 71, 710 66, 370366, 370367, 341100, 341101

Abstract:

A physical layer device (PLD) includes a first serializer-deserializer (SERDES) device and a second SERDES device. Each SERDES device includes an analog portion with a serial port that is configured to communicate serial data with various network devices, and a digital portion that is configured to communicate parallel data with other various network devices. The PLD includes a first signal path that is configured to route serial data signals between the analog portions of the SERDES devices, bypassing the digital portions of the SERDES devices. Therefore, the SERDES devices can directly communicate serial data without performing parallel data conversion. A second signal path is configured to route recovered clock and data signals between the analog portions of the SERDES devices, but still bypassing the digital portions of the SERDES devices. The recovered clock and data signals are then regenerated before being transmitted over a network device.

US Patent:

7362797, Apr 22, 2008

Filed:

Mar 21, 2003

Appl. No.:

10/392831

Inventors:

Kevin T Chan - Pasadena CA, US
Michael Q Le - Laguna Niguel CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H04B 1/38

US Classification:

375219

Abstract:

A physical layer device (PLD) includes a first serializer-deserializer (SERDES) device and a second SERDES device. Each SERDES device includes an analog portion with a serial port that is configured to communicate serial data with various network devices, and a digital portion that is configured to communicate parallel data with other various network devices. The PLD includes a first signal path that is configured to route serial data signals between the analog portions of the SERDES devices, bypassing the digital portions of the SERDES devices. Therefore, the SERDES devices can directly communicate serial data without performing parallel data conversion. A second signal path is configured to route recovered clock and data signals between the analog portions of the SERDES devices, but still bypassing the digital portions of the SERDES devices. The recovered clock and data signals are then regenerated before being transmitted over a network device. Signal latency and hardware requirements are reduced by bypassing the digital portions of the SERDES devices and avoiding the parallel conversion associated with the digital portions.

US Patent:

20090296868, Dec 3, 2009

Filed:

Aug 5, 2009

Appl. No.:

12/536186

Inventors:

Hui PAN - Irvine CA, US
Seong-Ho Lee - Aliso Viejo CA, US
Michael Q. Le - Laguna Niguel CA, US

Assignee:

BROADCOM CORPORATION - Irvine CA

International Classification:

H04L 7/00

US Classification:

375372

Abstract:

A system and method are used to allow for phase rotator control signals to be produced that rotate bits in the signals more than one step per clock cycle. This can be done through the following operation. First and second data signals that include a plurality of data bits are stored. Rotation of data bits in the first data signal and subsequently data bits in the second data signal is controlled based on a phase control signal during each clock cycle. The first and second controlled data signals are interleaved to form first and second interleaved data signals. One of the first and second interleaved data signals is selected based on a portion of the phase control signal during a second half of the clock cycle. Finally, the selected data signal is transmitted as the phase control signal.