Michael Mai Le

US Patent:

6509773, Jan 21, 2003

Filed:

Apr 30, 2001

Appl. No.:

09/844266

Inventors:

Aaron W. Buchwald - Newport Coast CA
Myles Wakayama - Laguna Niguel CA
Michael Le - Irvine CA
Jurgen Van Engelen - Aliso Viejo CA
Xicheng Jiang - Irvine CA
Hui Wang - Irvine CA
Howard A. Baumer - Laguna Hills CA
Avanindra Madisetti - Coto De Caza CA

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03H 1116

US Classification:

327248, 327361

Abstract:

A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

US Patent:

6791388, Sep 14, 2004

Filed:

Jan 17, 2003

Appl. No.:

10/346210

Inventors:

Aaron W. Buchwald - Newport Coast CA
Myles Wakayama - Laguna Niguel CA
Michael Le - Irvine CA
Jurgen Van Engelen - Aliso Viejo CA
Xicheng Jiang - Irvine CA
Hui Wang - Irvine CA
Howard A. Baumer - Laguna Hills CA
Avanindra Madisetti - Coto De Caza CA

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03H 1116

US Classification:

327248, 327361

Abstract:

A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

US Patent:

6995594, Feb 7, 2006

Filed:

May 28, 2004

Appl. No.:

10/855392

Inventors:

Aaron W. Buchwald - Newport Coast CA, US
Myles Wakayama - Laguna Niguel CA, US
Michael Le - Irvine CA, US
Jurgen Van Engelen - Aliso Viejo CA, US
Xicheng Jiang - Irvine CA, US
Hui Wang - Irvine CA, US
Howard A. Baumer - Laguna Hills CA, US
Avanindra Madisetti - Coto De Caza CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03H 11/16

US Classification:

327248, 327361

Abstract:

A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

US Patent:

7012983, Mar 14, 2006

Filed:

Apr 30, 2001

Appl. No.:

09/844296

Inventors:

Aaron W. Buchwald - Newport Coast CA, US
Myles Wakayama - Laguna Niguel CA, US
Michael Le - Irvine CA, US
Jurgen Van Engelen - Aliso Viejo CA, US
Xicheng Jiang - Irvine CA, US
Hui Wang - Irvine CA, US
Howard A. Baumer - Laguna Hills CA, US
Avanindra Madisetti - Coto De Caza CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03D 3/34
H04L 7/00

US Classification:

375373, 375354, 375376

Abstract:

A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

US Patent:

7016449, Mar 21, 2006

Filed:

Apr 30, 2001

Appl. No.:

09/844432

Inventors:

Aaron W. Buchwald - Newport Coast CA, US
Myles Wakayama - Laguna Niguel CA, US
Michael Le - Irvine CA, US
Jurgen Van Engelen - Aliso Viejo CA, US
Xicheng Jiang - Irvine CA, US
Hui Wang - Irvine CA, US
Howard A. Baumer - Laguna Hills CA, US
Avanindra Madisetti - Coto De Caza CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03D 3/24
H04L 7/00

US Classification:

375373, 375354, 375376

Abstract:

A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

US Patent:

7058150, Jun 6, 2006

Filed:

Apr 30, 2001

Appl. No.:

09/844441

Inventors:

Aaron W. Buchwald - Newport Coast CA, US
Michael Le - Irvine CA, US
Jurgen Van Engelen - Aliso Viejo CA, US
Xicheng Jiang - Irvine CA, US
Hui Wang - Irvine CA, US
Howard A. Baumer - Laguna Hills CA, US
Avanindra Madisetti - Coto De Caza CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H04L 7/00

US Classification:

375355, 375346, 375260, 375279, 375229, 370330, 370307, 439108, 439680

Abstract:

A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

US Patent:

7162002, Jan 9, 2007

Filed:

Oct 31, 2002

Appl. No.:

10/284341

Inventors:

Chun-Ying Chen - Irvine CA, US
Michael Q Le - Irvine CA, US
Myles Wakayama - Laguna Niguel CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03D 3/24

US Classification:

375376, 375362, 375373, 375374, 375375, 455260

Abstract:

A phase lock loop frequency synthesizer includes a phase rotator in the feedback path of the PLL. The PLL includes a phase detector, a low pass filter, a charge pump, a voltage controlled oscillator (“VCO”), and a feed back path connecting output of the VCO to the phase detector. The feedback path includes a phase rotator connected to the output of the VCO and to an input of a frequency divider. Coarse frequency control is implemented by adjusting the input reference frequency to the phase detector or by adjusting the divider ratio of the frequency divider. Fine frequency control is achieved by increasing or decreasing the rotation speed of the phase rotator. The phase rotator constantly rotates phase of the VCO output, thereby causing a frequency shift at the output of the phase rotator. The rotation speed of the phase rotator is controlled by an accumulator and a digital frequency control word. Any high frequency noise generated by the phase rotator is rejected by the PLL by properly setting the PLL bandwidth so that the noise falls outside the bandwidth of the PLL.

US Patent:

7336178, Feb 26, 2008

Filed:

Sep 20, 2005

Appl. No.:

11/231728

Inventors:

Michael Q. Le - Laguna Niguel CA, US

International Classification:

G08B 13/14

US Classification:

3405721, 340 101, 34053913

Abstract:

An apparatus and method for automatically tracking each individual vehicle, of a plurality of vehicles, in a race around a track. The device employs RFID tags on each of the vehicles being tracked and at gates adapted to cause the RFID to energize and broadcast the vehicle's identity when a pass through the gate is determined. Collisions of data transmission and resulting loss of identification data are reduced through commands to RFIDs responding and remedied with an inventory command based on most likely respondents. The device can be employed to both track the individual vehicle participants in a race and also to register the participants in the race. Races can be tracked on different courses in different geographic locations by placing the RFID tags on all participants and tracking their progress on the individual remote tracks from a central location.