Michael J Leary

US Patent:

53534247, Oct 4, 1994

Filed:

Nov 19, 1991

Appl. No.:

7/794865

Inventors:

Hamid Partovi - Westboro MA
William R. Wheeler - Hudson MA
Michael Leary - Jefferson MA
Michael A. Case - Grafton MA
Steven Butler - Marlboro MA
Rajesh Khanna - Westboro MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 1208

US Classification:

395425

Abstract:

A tag comparator and bank selector for a set-associative cache in a computer system operates in a minimum time so that a cache hit or miss signal is generated early in a memory cycle. The data memory of the cache has two (or more) banks, with a tag store for each bank, and the two banks are accessed separately and in parallel using the index (low order address bits) while the tag translation is in progress. Two bit-by-bit tag compares are performed, one for each tag store, producing two multibit match indications, one bit for each tag bit in each tag store. These two match indications are applied to two separate dynamic NOR gates, and the two outputs applied to a logic circuit to detect a hit and generate a bank-select output. There are four possible outcomes from the compare operation: both banks miss, left bank hits, right bank hits, and both banks hit. The later condition indicates a possible ambiguity, and neither data item should be used, so a miss is signalled.