Michael H Liu

US Patent:

6775178, Aug 10, 2004

Filed:

Apr 4, 2002

Appl. No.:

10/116296

Inventors:

Michael S. Liu - Bloomington MN
Shankar P. Sinha - Redwood City CA

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

G11C 1100

US Classification:

365154, 36518507, 365205, 365156, 365190

Abstract:

A random access memory cell has first and second inverters each having an input and an output. The input of the first inverter is coupled to the output of the second inverter by a Schottky-diode-free MOSFET. The input of the second inverter is coupled to the output of the first inverter.

US Patent:

7200031, Apr 3, 2007

Filed:

Mar 16, 2005

Appl. No.:

11/082161

Inventors:

Michael Liu - Bloomington MN, US
Harry Liu - Plymouth MN, US

Assignee:

Honeywell International, Inc. - Morristown NJ

International Classification:

G11C 11/00

US Classification:

365154, 365156, 365190, 365 1

Abstract:

A method and system is disclosed for reducing proton and heavy ion SEU sensitivity of a static random access memory (SRAM) cell. A first passive delay element has been inserted in series with an active delay element in a first feedback path of the SRAM cell, and a second passive delay element has been inserted in a second feedback path of the SRAM cell. The passive delay elements reduce the proton SEU sensitivity of the SRAM cell, and the active delay element reduces the heavy ion sensitivity of the SRAM cell. The passive delay elements also protect the SRAM cell against SEUs that may occur when the SRAM cell is in dynamic mode.

US Patent:

7322015, Jan 22, 2008

Filed:

Jan 5, 2005

Appl. No.:

11/029308

Inventors:

Harry H. L. Liu - Plymouth MN, US
Keith W. Golke - Minneapolis MN, US
Eric E. Vogt - Minneapolis MN, US
Michael S. Liu - Bloomington MN, US

Assignee:

Honeywell Internatinal Inc. - Morristown NJ

International Classification:

G06F 17/50
G06G 7/62

US Classification:

716 4, 703 14

Abstract:

Behaviors of a transistor during a dose rate event can be modeled using a circuit simulation software package. A subcircuit model replaces a transistor in a circuit design to be simulated. The subcircuit model can be in the form of a schematic-based representation or a netlist. The subcircuit model provides a model of a source junction and a drain junction in the transistor during the dose rate event. The subcircuit model also includes the size of the transistor being replaced and the dose rate of the dose rate event. Once the transistor is replaced with the subcircuit model, a dose rate simulation may be performed to determine the dose rate hardness of the circuit design.

US Patent:

7589308, Sep 15, 2009

Filed:

Sep 1, 2006

Appl. No.:

11/469803

Inventors:

Harry H L Liu - Maple Grove MN, US
Anuj Kohli - Apple Valley MN, US
Michael S Liu - Bloomington MN, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

H01J 40/14
H01L 23/62

US Classification:

250214R, 257351, 257355

Abstract:

A method and apparatus for regulating photocurrents is described. A photocurrent regulator may include a transistor having an associated cross-sectional area. The photocurrent regulator is coupled between an integrated circuit and a voltage source. When a dose rate event occurs within the integrated circuit, the photocurrent regulator, via the cross-sectional area, regulates a recombination path to the voltage source. Consequently, photocurrents within the integrated circuit are regulated, preventing permanent damage within the integrated circuit.

US Patent:

20030189227, Oct 9, 2003

Filed:

Apr 4, 2002

Appl. No.:

10/116295

Inventors:

Michael Liu - Bloomington MN, US
Shankar Sinha - Redwood City CA, US
Jane Rekstad - Maple Grove MN, US
Paul Fechner - Plymouth MN, US

Assignee:

Honeywell International Inc.

International Classification:

H01L027/01
H01L027/12
H01L031/0392

US Classification:

257/347000

Abstract:

An SOI GAA device is created by etching a buried oxide layer of an SOI wafer structure that is provided over a silicon substrate. A portion of the buried oxide layer remains over the silicon substrate after etching. A plurality of silicon fingers is formed so that the silicon fingers extend over the remaining buried oxide layer. A gate oxide is formed all around each of the silicon fingers, and a common silicon gate is formed all around all of the gate oxides. A common source and a common drain are formed by suitably doping opposite ends of the silicon fingers leaving a channel therebetween.

US Patent:

20040030428, Feb 12, 2004

Filed:

May 5, 2003

Appl. No.:

10/429235

Inventors:

Myrick Crampton - Mt. Pleasant SC, US
Michael Liu - Germantown MD, US
Jay Harrison - Mount Airy MD, US

Assignee:

Manugistics, Inc.

International Classification:

G06F019/00

US Classification:

700/101000

Abstract:

The present invention optimizes shop floor operations by generating production schedules that respect the complex manufacturing rules of specified production operations. The invention utilizes attribute-sensitive changeover models that consider both the duration and cost of each changeover. Since the invention considers more than just the item, changeover models can be based at the item level and the item attribute level. The invention includes realistic models that simulate operations for a variety of process and discrete manufacturing work centers and departments. These models support reusable and auxiliary resources, resource groups, user-defined units of measure, detailed bills of material (BOMs), production rate models, and production method models. The sequencing invention can be integrated with other planning optimization systems, including planning and scheduling engines, to provide further shop floor optimization to productively drive the sequencing of a complex business.

US Patent:

20070242537, Oct 18, 2007

Filed:

Mar 27, 2006

Appl. No.:

11/389767

Inventors:

Keith Golke - Minneapolis MN, US
Harry Liu - Maple Grove MN, US
Michael Liu - Bloomington MN, US
David Nelson - Medicine Lake MN, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

G11C 7/00

US Classification:

365194000

Abstract:

A radiation hardened memory element includes at least two delay elements for maintaining radiation hardness. In an example, the memory element is an SRAM cell. Both delays are coupled together in series so that if either one of the delays fails, a delay will still be maintained within the SRAM cell. The critical areas of the delays may be positioned so that a common line of sight cannot be made between each delay and a circuit node.

US Patent:

52602257, Nov 9, 1993

Filed:

Nov 9, 1992

Appl. No.:

7/973606

Inventors:

Michael S. Liu - Bloomington MN
Jeffrey S. Haviland - Plymouth MN
Cheisan J. Yue - Roseville MN

Assignee:

Honeywell Inc. - Minneapolis MN

International Classification:

H01L 318

US Classification:

437 3

Abstract:

A method for fabricating an integrated infrared sensitive bolometer having a polycrystalline element whereby an oxide region deposited on silicon nitride covered with a first polysilicon layer which is etched to provide a location for a bolometer element. A second polysilicon layer is deposited and doped to achieve a desired temperature coefficient of resistivity of 1 to 2%/. degree. C. The second polysilicon layer forms an IR sensitive element over the oxide region. Openings are etched in the IR sensitive element to permit an etchant to remove the oxide region resulting in the sensitive element being suspended over a cavity.