Michael Y Liu

US Patent:

6829660, Dec 7, 2004

Filed:

Dec 10, 2002

Appl. No.:

10/316604

Inventors:

Michael Liu - Alhambra CA
Bradley Roach - Newport Beach CA
Sam Su - Irvine CA
Peter Fiacco - Yorba Linda CA

Assignee:

Emulex Design Manufacturing Corporation - Costa Mesa CA

International Classification:

G06F 1328

US Classification:

710 22, 710 38, 710305, 709212

Abstract:

A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from atleast two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.

US Patent:

7096296, Aug 22, 2006

Filed:

Nov 22, 2004

Appl. No.:

10/995456

Inventors:

Michael Liu - Alhambra CA, US
Bradley Roach - Newport Beach CA, US
Sam Su - Irvine CA, US
Peter Fiacco - Yorba Linda CA, US

Assignee:

Emulex Design & Manufacturing Corporation - Costa Mesa CA

International Classification:

G06F 13/24
G06F 13/32

US Classification:

710260, 710 15, 710 18, 710 19, 710 48, 710 52, 710261, 710263, 710267

Abstract:

A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from at least two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.

US Patent:

7937188, May 3, 2011

Filed:

May 23, 2007

Appl. No.:

11/805581

Inventors:

Michael Yu Liu - Costa Mesa CA, US
Bradley Eugene Roach - Costa Mesa CA, US
Vuong Cao Nguyen - Costa Mesa CA, US
Peter Mark Fiacco - Costa Mesa CA, US
Shak Loong Kwok - Costa Mesa CA, US

Assignee:

Emulex Design & Manufacturing Corporation - Costa Mesa CA

International Classification:

G06F 15/00

US Classification:

700299, 710 10, 702132, 713300, 709221

Abstract:

Embodiments of the present invention are directed to systems and methods for controlling the temperature of an internal device while reducing or minimizing the involvement of the host. Thus, some of the heat monitoring and remediation work may be offloaded to the actual device itself. The device may monitor its own temperature and, in the event of high temperature, perform device specific heat reduction actions without involving the host. Furthermore, the device may, upon detecting temperature within a predefined range, alert the host of a high temperature condition in order to allow the host to perform temperature reduction measures. Also, the device may, upon detecting temperature within a predefined range, alert the host of an impending device shutdown and shut the device down. In addition, the device may periodically save its temperature into non-volatile memory in order to create a temperature log.

US Patent:

7363396, Apr 22, 2008

Filed:

Feb 24, 2006

Appl. No.:

11/361344

Inventors:

Michael Liu - Alhambra CA, US
Bradley Roach - Newport Beach CA, US
Sam Su - Irvine CA, US
Peter Fiacco - Yorba Linda CA, US

Assignee:

Emulex Design & Manufacturing Corporation - Costa Mesa CA

International Classification:

G06F 13/12
G06F 3/00
G06F 13/28

US Classification:

710 20, 710 1, 710 5, 710 21, 710 22, 710 29, 710 36, 710 38, 710 62, 710 72, 710305, 710306, 710308, 710311, 700 1, 700 2, 700 4, 709206, 709207, 709212, 709213, 709217, 709250

Abstract:

A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from at least two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.

US Patent:

20100057472, Mar 4, 2010

Filed:

Oct 9, 2008

Appl. No.:

12/248506

Inventors:

Hanks Zeng - Red Bank NJ, US
Nelson Sollenberger - Farmingdale NJ, US
Radhakrishnan Kuzhipatt - Irvine CA, US
Michael Liu - Sunnyvale CA, US
Taiyi Cheng - San Jose CA, US
Hongwei Kong - Denville NJ, US

International Classification:

G10L 21/00

US Classification:

704500, 704E19001

Abstract:

In a method and system for frequency compensation in an audio CODEC, a filter in a hardware audio CODEC may be configured based on power consumption and based on a frequency response of an active output device to which the filter is communicatively coupled. The filter may comprise a plurality of filter stages, which may be, for example, biquads, and the filter may be configured by enabling or disabling one or more of the stages. In this manner, power consumption of the filter may be managed by enabling and/or disabling one or more stages. Configuration of the filter may be performed dynamically depending on whether one or more audio output devices may be active. In this regard, which output device is active and its frequency response may be determined and filter coefficients may be reconfigured upon a change in which output device may be active.

US Patent:

20100064072, Mar 11, 2010

Filed:

Sep 9, 2008

Appl. No.:

12/207380

Inventors:

John Sui-kei Tang - Costa Mesa CA, US
Sam Shan-Jan Su - Costa Mesa CA, US
Michael Yu Liu - Costa Mesa CA, US
Daming Jin - Costa Mesa CA, US

Assignee:

Emulex Design & Manufacturing Corporation - Costa Mesa CA

International Classification:

G06F 13/28

US Classification:

710 39

Abstract:

A network arbitration scheme is disclosed that manages device access fairness by selectively and dynamically increasing a requestor queue's likelihood of being serviced. A requestor queue increases its service priority by duplicating a request entry onto a set of priority rings maintained by arbitration hardware in a host bus adapter. Duplication occurs when (1) a requestor's queue fill count (the number of descriptors stored in the queue) exceeds a watermark level or (2) a requestor's queue timer times out. In the case of time-out, the requester in the lower priority ring will duplicate itself in the higher priority ring. Because the arbitration hardware services requesters using a round robin selection scheme, the likelihood of a requestor queue being serviced increases as the number of its duplicate request entries on a priority ring increases. Upon being serviced, the requester is able to perform the requested action.