Mike J Erickson

US Patent:

6918027, Jul 12, 2005

Filed:

Jul 30, 2001

Appl. No.:

09/917983

Inventors:

Paul Mantey - Ft. Collins CO, US
Mike Erickson - Loveland CO, US
David Maciorowski - Parker CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F013/10

US Classification:

712 37

Abstract:

A system, such as a complex computer system, incorporates several programmable logic devices coupled to load their configuration code from associated EEPROMs; typically this load is automatic on powerup. The EEPROMs connect to one of several serial busses, typically JTAG busses, connecting the EEPROMs with a common configuration logic. A processor is configured to write programmable logic configuration code from its memory through the common configuration logic and over the serial busses into the EEPROMs. The processor is also capable of connecting to a network and fetching configuration code for writing to the EEPROMs.

US Patent:

7039736, May 2, 2006

Filed:

Jan 15, 2003

Appl. No.:

10/342886

Inventors:

Paul J. Mantey - Fort Collins CO, US
Mike J. Erickson - Loveland CO, US
David R. Maciorowski - Longmont CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 13/36
G06F 13/368
G06F 12/00
G06F 13/00
G06F 11/00

US Classification:

710113, 710119, 710240, 710241, 710242, 710243, 710316, 710317, 370217, 370221, 370225

Abstract:

Disclosed are systems and methods for providing access to bus-mastered system resources comprising disposing a bus multiplexer between a first bus and a bus access arbiter, wherein the first bus is coupled to at least one system resource for which bus access is arbitrated by the bus access arbiter, and controlling the bus multiplexer to couple a second bus to the first bus thereby providing a link between the first bus and the second bus bypassing the bus access arbiter.

US Patent:

20040042034, Mar 4, 2004

Filed:

Sep 3, 2002

Appl. No.:

10/233967

Inventors:

Jeff Tiffan - Greeley CO, US
Jeff Wiley - Greeley CO, US
Mike Erickson - Fort Collins CO, US

International Classification:

G06F013/00
G06F015/00

US Classification:

358/001150, 358/001200

Abstract:

A communications device for distributing an image of a paper document to a plurality of recipients having a database comprising a preferred electronic format of each of the recipients and an imaging device for converting the paper document into the preferred electronic format for each recipient in the database prior to distribution of the document in the preferred electronic format.

US Patent:

20040158424, Aug 12, 2004

Filed:

Feb 11, 2003

Appl. No.:

10/364858

Inventors:

Paul Mantey - Ft. Collins CO, US
Mike Erickson - Loveland CO, US

International Classification:

G06F019/00

US Classification:

702/122000

Abstract:

A field replaceable unit has a connector with first and second interconnect apparatus coupled to connector. The field replaceable unit has test apparatus coupled to the first and second interconnect apparatus capable of testing connections through the connector to the first interconnect apparatus under control of signals on the second interconnect apparatus. The field replaceable unit is capable of being hot-plugged. In an embodiment, the second interconnect apparatus is of the JTAG type. Also claimed is a method of testing interconnect between the field replaceable unit and another unit of a system into which it has been hot-plugged.

US Patent:

20060209507, Sep 21, 2006

Filed:

Mar 17, 2005

Appl. No.:

11/084590

Inventors:

S. Sidle - Fort Collins CO, US
Mike Erickson - Loveland CO, US
Raymond Woodward - Windsor CO, US

International Classification:

G06F 1/16

US Classification:

361685000

Abstract:

A media holding device for connecting an electronic component to a computer is described herein. An embodiment of the device comprises a bay comprising a bay first side and a bay second side, wherein the electronic component is receivable in the bay first side. The media holding device may also comprise a first circuit comprising a first connector and a second connector. The first connector is located proximate the bay second side. A third connector associated with the electronic component is connectable to the first connector when the electronic component is received within the bay. A connector associated with the computer is connectable to the second connector. The circuit translates a first data protocol transmitted by way of the first connector to a second data protocol transmitted by way of the second connector. The media holding device may further comprise a release member, wherein the release member is movable relative to the bay. The release member is in a first position when it is located in a first position relative to the bay and wherein the first release member is in a second position when it is in a second position relative to the bay. Movement of the first release member from the first position to the second position causes the first connector to disconnect from the third connector.

US Patent:

20110145655, Jun 16, 2011

Filed:

Dec 11, 2009

Appl. No.:

12/635894

Inventors:

Mike ERICKSON - Fort Collins CO, US
David MACIOROWSKI - Longmont CO, US

International Classification:

G06F 13/42
G06F 13/00
G06F 11/07

US Classification:

714 43, 710105, 710302, 714E11024

Abstract:

Example apparatus and methods virtualize a circuit disposed between an input/output (I/O) hub and an I/O device. The I/O hub is configured to communicate PCIe slot control and status signals with an I/O device via an interface. The example apparatus and methods selectively intercept and transform signals passing between the I/O hub and the I/O device. The example apparatus and methods may also provide intercepted signals to a sideband monitor.

US Patent:

20120331196, Dec 27, 2012

Filed:

Feb 26, 2010

Appl. No.:

13/387186

Inventors:

Mike Erickson - Fort Collins CO, US
David Maciorowski - Longmont CO, US

International Classification:

G06F 13/00

US Classification:

710110, 710107

Abstract:

A method for restoring stability to an unstable bus includes cycling a clock of the bus a number of times, transmitting a stop bit, cycling a clock line of the bus at least one time and transmitting a stop bit immediately after an acknowledgment bit has been received by a bus master.