Mirza M Jahan from 1633 Crescent Ct, Chandler, AZ 85249, Phone: 4808023141

Resumes

Senior Principal Engineer

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Location:

Chandler, AZ

Industry:

Semiconductors

Work:

Intel Corporation 2005 - 2013
Principal Engineer
Intel Corporation 2005 - 2013
Senior Principal Engineer
Intel Corporation 1996 - 2005
Design Manager
Intel Corporation 1995 - 1996
Component Design Engineer

Education:

University of Connecticut 1992 - 1995
Doctorates, Doctor of Philosophy, Electronics Engineering, Philosophy University of Connecticut 1991 - 1992
Master of Science, Masters, Electronics Engineering Bangladesh University of Engineering and Technology 1984 - 1989
Bachelors, Bachelor of Science, Electronics Engineering

Skills:

Semiconductors
Low Power Design
Circuit Design
Processors
Microprocessors
Soc
System on A Chip
Integrated Circuits
Application Specific Integrated Circuits
Embedded Systems
Very Large Scale Integration
Verilog
Static Timing Analysis
Semiconductor Process Technology

Mirza Jahan

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Us Patents

Method And Apparatus For Dynamically Controlling The Performance Of Buffers Under Different Performance Conditions
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US Patent:

6566903, May 20, 2003
Filed:

Dec 28, 1999
Appl. No.:

09/474047
Inventors:

Subrata Mandal - Orangevale CA
Mirza Jahan - Citrus Heights CA
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H03K 1716
US Classification:

326 30, 326 26, 327281
Abstract:

According to one aspect of the invention, a method is provided in which an input signal is received at a first node of a buffer circuit. The propagation of the input signal from the first node to a second node in the buffer circuit is delayed by a delay period based upon a first control input. The delay period is adjusted by a factor based upon a second control input.

Method And Apparatus For Dynamically Controlling The Performance Of Buffers Under Different Performance Conditions
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US Patent:

6624655, Sep 23, 2003
Filed:

Dec 9, 2002
Appl. No.:

10/315973
Inventors:

Subrata Mandal - Orangevale CA
Mirza Jahan - Citrus Heights CA
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H03K 1716
US Classification:

326 30, 326 26, 327281
Abstract:

According to one aspect of the invention, a method is provided in which an input signal is received at a first node of a buffer circuit. The propagation of the input signal from the first node to a second node in the buffer circuit is delayed by a delay period based upon a first control input. The delay period is adjusted by a factor based upon a second control input.

Low-Leakage Level Shifter With Integrated Firewall And Method
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US Patent:

7129751, Oct 31, 2006
Filed:

Jun 28, 2004
Appl. No.:

10/880767
Inventors:

Mirza M. Jahan - Chandler AZ, US
Noor E. Sarwar - Chandler AZ, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H03K 19/0175
H03K 19/094
US Classification:

326 68, 326 63, 327333
Abstract:

A level shifter may reduce leakage current and provide firewall protection between circuits of different voltage domains when one voltage domain is in a standby mode. The level shifter may either couple or decouple input circuitry from a reference voltage in response to a firewall enable signal, may translate signals between a first voltage domain and a second voltage domain when the firewall enable signal is deasserted, and may generate an output signal having a predetermined one of either a high or low state when the firewall enable signal is asserted.

Low-Leakage Level Shifter With Integrated Firewall And Method
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US Patent:

7342417, Mar 11, 2008
Filed:

Jul 28, 2006
Appl. No.:

11/460885
Inventors:

Mirza M. Jahan - Chandler AZ, US
Noor E. Sarwar - Chandler AZ, US
Assignee:

Marvell International Ltd. - Hamilton
International Classification:

H03K 19/0175
H03K 19/094
US Classification:

326 68, 326 63, 327333
Abstract:

A level shifter may reduce leakage current and provide firewall protection between circuits of different voltage domains when one voltage domain is in a standby mode. The level shifter may either couple or decouple input circuitry from a reference voltage in response to a firewall enable signal, may translate signals between a first voltage domain and a second voltage domain when the firewall enable signal is deasserted, and may generate an output signal having a predetermined one of either a high or low state when the firewall enable signal is asserted.

Low-Leakage Level Shifter With Integrated Firewall And Method
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US Patent:

7471106, Dec 30, 2008
Filed:

May 15, 2007
Appl. No.:

11/798602
Inventors:

Mirza Jahan - Chandler AZ, US
Noor Sarwar - Chandler AZ, US
Assignee:

Marvell International Ltd. - Hamilton
International Classification:

H03K 19/0175
US Classification:

326 68, 326 63, 327333
Abstract:

A level shifter may reduce leakage current and provide firewall protection between circuits of different voltage domains when one voltage domain is in a standby mode. The level shifter may either couple or decouple input circuitry from a reference voltage in response to a firewall enable signal, may translate signal having a predetermined one of either a high or low state when the firewall enable signal is asserted.

Utilization Of Scan Structures And On-Chip Memory For Retaining Block State Information During Power Down
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US Patent:

20080155170, Jun 26, 2008
Filed:

Dec 22, 2006
Appl. No.:

11/644510
Inventors:

Mirza M. Jahan - Chandler AZ, US
Rajagopalan Srinivasan - El Dorado Hills CA, US
Manish Dandekar - Roseville CA, US
International Classification:

G06F 12/00
US Classification:

711100, 711E12001
Abstract:

A method, system and apparatus to retain the state of a block in a local memory utilizing the block's scan structures. A controller may configure the scan chains and may enable the transfer of state information between the block and the local memory.

Method And Apparatus For Improving The Performance Of Buffers Using A Translator Circuit
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US Patent:

6426651, Jul 30, 2002
Filed:

Jun 28, 2000
Appl. No.:

09/605126
Inventors:

Subratakumar Mandal - Orangevale CA
Mirza Jahan - Folsom CA
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H03K 190175
US Classification:

326 63, 326 30, 326 87
Abstract:

According to one aspect of the invention, a method is provided in which an input signal is received at a first node of a buffer. The input signal is strengthened by a factor that corresponds to a control signal. The control signal is derived from an output signal of an impedance control unit that is used to compensate for variations in the buffers performance conditions. The output signal of the impedance control unit has a range of values corresponding to variations in the buffers performance conditions. The control signal has a range of values that is larger than the range of values associated with the output signal of the impedance control unit.