Patrick W Mccabe

US Patent:

7579972, Aug 25, 2009

Filed:

Nov 30, 2007

Appl. No.:

11/948546

Inventors:

David George Copeland - Palm Harbor FL, US
Patrick Arthur McCabe - Crystal Beach FL, US
Rocky Ardy Ilen - Tampa FL, US
Jonathan Borui Kang - Tampa FL, US

Assignee:

ITT Manufacturing Enterprises, Inc. - Wilmington DE

International Classification:

H03M 1/66

US Classification:

341144, 341145, 341101, 341152

Abstract:

An RFIC controller configured for executing multiple tasks. A serial interface is included having a serial bus for receiving a data stream having control bits and data bits. One or more registers are coupled to the serial bus for storing the control bits and data bits as they are received. Control circuitry is also included. The data stream is formatted such that the control bits are received before the data bits, the control bits specifying an operation. The control circuitry is configured to examine the control bits as they are received to determine the operation specified by the control bits before the data bits are received. A task corresponding to the operation specified by the control bits is then initiated before the data bits are received.

US Patent:

8027420, Sep 27, 2011

Filed:

Mar 19, 2008

Appl. No.:

12/051067

Inventors:

Patrick A. McCabe - Crystal Beach FL, US

Assignee:

ITT Manufacturing Enterprises, Inc. - Wilmington DE

International Classification:

H04L 7/00
H04L 23/00

US Classification:

375354, 375377

Abstract:

A circuit is provided for transferring a signal from a fast clock domain to a slow clock domain. The circuit includes a fast clock domain configured to receive an input signal and, responsively, transfer an intermediate signal. The circuit also a slow clock domain configured to receive the transferred intermediate signal from the fast clock domain and, responsively, generate an output signal. The circuit further includes a first synchronizer disposed in the slow clock domain and a second synchronizer disposed in the fast clock domain. The first synchronizer, operating with a slow clock, is configured to receive the intermediate signal and, responsively, provide the output signal as a transferred signal which is synchronized to the input signal. The second synchronizer, operating with a fast clock, is configured to receive a feedback signal from the first synchronizer for acknowledging synchronization of the output signal to the input signal.

US Patent:

8078829, Dec 13, 2011

Filed:

Dec 12, 2007

Appl. No.:

11/954859

Inventors:

Patrick Arthur McCabe - Crystal Beach FL, US

Assignee:

ITT Manufacturing Enterprises, Inc. - Wilmington DE

International Classification:

G06F 15/00

US Classification:

712 10

Abstract:

A system for implementing waveform processing in a software defined radio (SDR) includes a scaleable array processor having a plurality of micro-engines (MEs) interconnected by a two dimensional topology. Each micro-engine includes multiple FIFOs for interconnecting to each other in the two dimensional topology. One micro-engine communicates with another adjacent micro-engine by way of the respective FIFOs. The micro-engines are dedicated to predetermined algorithms. The two dimensional topology includes an array of N×M micro-engines interconnected by the multiple FIFOs. The N×M are integer numbers of rows and columns, respectively, in the array of micro-engines. The micro-engines are dedicated to baseband processing of data for RF transmission or RF reception.

US Patent:

8438951, May 14, 2013

Filed:

Apr 27, 2010

Appl. No.:

12/768009

Inventors:

Patrick A. McCabe - Crystal Beach FL, US
Mark Jeffrey Hornick - Lutz FL, US
Eliot Thomas Dill - Mulberry FL, US
Michael Wood - Inverness FL, US
Dean A. Collura - Wesley Chapel FL, US

Assignee:

University of South Florida - Tampa FL

International Classification:

B67B 7/18
B67B 7/44

US Classification:

81 332, 7151, 81 34, 81 329, 81 309

Abstract:

A pill bottle opener including a base, a utility ring, and a cap. The utility ring includes two tabs positioned in its inner portion. The cap has a hollow, cylindrical body open on one end and has a dome-shaped top on its other end. The utility ring and cap may be interlocked by a locking mechanism.

US Patent:

62086502, Mar 27, 2001

Filed:

Apr 2, 1998

Appl. No.:

9/054194

Inventors:

Suzanne Hassell - Clearwater FL
Patrick A. McCabe - Palm Harbor FL
Louis F. Villarosa - Tampa FL
Jeffrey E. Conner - Clearwater FL

Assignee:

Paradyne Corporation - Largo FL

International Classification:

H04L12/56

US Classification:

370392

Abstract:

The present invention is a hardware implementation of frame relay switching functions which provides for real time concurrent multiple processes by implementing the processes in dedicated hardware logic operating in parallel, whereas in a typical software implementation the processes are sequentially processed. While data structures in software based implementations are accessed on some multiple of a byte regardless of the logical structure of the data, in the hardware implementation of the present invention the physical widths and the logical widths of the data structure elements are identical. This allows direct access of the logical structure by the operating process.