Paul W Hunter

US Patent:

50579975, Oct 15, 1991

Filed:

Feb 13, 1989

Appl. No.:

7/310409

Inventors:

Tai-Lin Chang - San Jose CA
Paul W. Hunter - San Jose CA
Donald J. Lang - Cupertino CA
Stephen G. Luning - San Jose CA

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

G06F 946

US Classification:

364200

Abstract:

In a programmed machine, such as an peripheral controller, programmed operations are executed in a one of several operational contexts. Each context may be initiated by a corresponding interruption signal. Any context which has been activated remains active until quiesced by program execution. One of the active contexts is a current context in which all instruction executions are currently occurring. In each cycle of the programmed machine, all active contexts and received and stored interruption signals, each for respective ones of the contexts, are compared to find the context highest priority context. Such highest priority context is compared with the current context priority for determining whether or not the programmed machine should change current contexts.

US Patent:

49691201, Nov 6, 1990

Filed:

Feb 13, 1989

Appl. No.:

7/310406

Inventors:

Michael J. Azevedo - San Jose CA
Paul W. Hunter - San Jose CA
Donald J. Lang - Cupertino CA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 900

US Classification:

364900

Abstract:

An access control or arbitrator for a shared resource, such as a time-slotted bus, groups requests according to priorities of the requests. The time slots are grouped into sets, each set having a number of successive time slots equal to the number of sources supplying access requests having a highest priority. In a highest priority group, each source supplying a highest priority access request is guaranteed access in respective ones of said time slots in each set of time slots. When any time slot is not being used by a high priority request, low priority requests then have access to the unused time slot. Lower priority groups of access requests are handled in accordance with a different algorithm, such as a round robin priority algorithm.

US Patent:

54329299, Jul 11, 1995

Filed:

Sep 9, 1992

Appl. No.:

7/942700

Inventors:

Dennis R. Escola - Gilroy CA
Steven D. Gerdt - San Jose CA
Barrie N. Harding - San Jose CA
Paul W. Hunter - San Jose CA
Lloyd R. Shipman - San Jose CA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1540

US Classification:

395600

Abstract:

A data storage and retrieval system is described having one or more key-lock storage areas which can be modified under the control of commands received from an attached computer. Each key-lock is stored in nonvolatile data storage. A key-lock contains a key field and a lock field. The contents of the key-lock are read and modified based on commands received from the computer. The command to write a new key-lock value specifies a first key and a proffered key-lock. The subsystem reads the current key-lock from nonvolatile storage, then compares the first and current keys. When the first and current keys are equal, the proffered key-lock is stored in the key-lock storage area of nonvolatile data storage, thereby replacing the original key-lock. When the keys are not equal, the key-lock is left unmodified and status data is transmitted to the computer indicating that the update request has failed. The subsystem will send the original key-lock value to the computer upon demand.

US Patent:

43108822, Jan 12, 1982

Filed:

Dec 28, 1978

Appl. No.:

5/973827

Inventors:

Paul W. Hunter - San Jose CA
Alexander E. Malaccorto - San Jose CA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

364200

Abstract:

A method and means are provided to increase the effective data transfer rate between a direct access storage device (DASD) and a central processing unit (CPU) communicating with the DAS device through a channel and a DASD control device. A command issued to the AS subsystem which requires mechanical motion in the DAS device is stored in the subsystem and the subsystem provides a response to the channel indicating that the command has been carried out, without actually carrying out the command. The channel responds by issuing one or more additional commands in the chain to the subsystem which may be carried out without mechanical motion. When a command is issued to the subsystem which again requires mechanical motion of the device, the control device causes the stored command to be executed essentially simultaneously with the newly received command. This execution of the stored command out of its normal sequence and in parallel with another command involving mechanical motion of the DAS device decreases the time required to perform operations with the DASD subsystem.

US Patent:

52851524, Feb 8, 1994

Filed:

Mar 23, 1992

Appl. No.:

7/855437

Inventors:

Paul W. Hunter - San Jose CA

Assignee:

MiniStar Peripherals International Limited - San Jose CA

International Classification:

G01R 1512

US Classification:

324158R

Abstract:

Apparatus for observing circuit nodes in an analog integrated circuit includes a multiplexer connected to a plurality of circuit nodes to be observed, a sample/hold circuit for holding voltages obtained from the selected nodes, and a controller responsive to external signals for controlling the operation of the multiplexer and the sample/hold circuit.

US Patent:

51558149, Oct 13, 1992

Filed:

Aug 31, 1990

Appl. No.:

7/575735

Inventors:

Brent C. Beardsley - Tucson AZ
Keith A. Bello - Tucson AZ
Michael T. Benhase - Tucson AZ
Florence J. Clark - Tucson AZ
Paul W. Hunter - San Jose CA
Donald M. Nordahl - Tucson AZ

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1312

US Classification:

395275

Abstract:

A control unit for DASD operation to transfer data between the device and a buffer and between a channel and a buffer. In that manner the channel and device are enabled to transfer data independently of each other. Mechanisms are provided for communication between the channel interface process in the control unit and the device interface process in the control unit. Some of these mechanisms are stored with the record in the buffer and others are stored in control storage. Principle communicating mechanisms include a device record pointer, a channel record pointer, a next operation field, a device state indicator, record control flags, and two buffer pointers.

US Patent:

56757360, Oct 7, 1997

Filed:

Jul 24, 1996

Appl. No.:

8/685770

Inventors:

James Thomas Brady - San Jose CA
Damon W. Finney - San Jose CA
Michael Howard Hartung - Tucson AZ
Paul Wayne Hunter - San Jose CA
Michael Anthony Ko - San Jose CA
Donald J. Lang - Cupertino CA
Noah R. Mendelsohn - Lexington MA
Jaishankar Moothedath Menon - San Jose CA
David Ronald Nowlen - Morgan Hill CA

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

39520003

Abstract:

A distributed data processing system includes a plurality of nodes interconnected by bidirectional communication links. Each node includes a control message line for handling of control messages and a control memory for storing the control messages. Each node further includes data message line for handling of data messages and a data memory for storing the data messages. A processor in the node causes the data message line to queue and dispatch data messages from the data memory and the control message line to queue and dispatch control messages from the control memory. Each node includes N bidirectional communication links enabling the node to have at least twice as much input/output bandwidth as the control message line and data message line, combined. An input/output switch includes a routing processor and is coupled between the N bidirectional communication links, the data message line and control message line. The input/output switch dispatches either a control message or a data message over at least one of the bidirectional communication links in accordance with an output from the routing control processor, thereby enabling each communication link to carry either data or control messages.

US Patent:

54164095, May 16, 1995

Filed:

Sep 8, 1993

Appl. No.:

8/117956

Inventors:

Paul W. Hunter - San Jose CA

Assignee:

MiniStor Peripherals International Limited - San Jose CA

International Classification:

G01R 1512

US Classification:

3241581

Abstract:

Apparatus for testing the integrity of a plurality of conductive circuit connection paths between output pins on a first integrated circuit and input pins on a second integrated circuit on a circuit board includes first boundary scan cells associated with each output pin on the first integrated circuit, each of the first boundary scan cells adapted to selectively place a data test bit loaded therein onto the one of the output pins with which it is associated, second boundary scan cells associated with each input pin on the second one of the integrated circuits, each of the second boundary scan cells adapted to selectively store the digital value present on the one of the input pins with which it is associated, a controller for loading a data test bit into each of the boundary scan cells associated with each output pin on the first one of the integrated circuits, for respectively placing each of the data test bits onto respective ones of the output pins of the first integrated circuit, for selectively storing into each of the second boundary scan cells in the second integrated circuit the digital values present on the ones of the input pins associated therewith, and for comparing the digital values with the data test bits. Apparatus for observing circuit nodes in an analog integrated circuit includes a multiplexer connected to a plurality of circuit nodes to be observed, a sample/hold circuit for holding voltages obtained from the selected nodes, and a controller responsive to external signals for controlling the operation of the multiplexer and the sample/hold circuit.