Paul Te Song

US Patent:

20140017317, Jan 16, 2014

Filed:

May 31, 2013

Appl. No.:

13/907726

Inventors:

Niven Rajin Narain - Cambridge MA, US
John Patrick McCook - Frisco TX, US
Paul Y. Song - Santa Monica CA, US
Ines Macias-Perez - Hermitage TN, US

International Classification:

A61K 31/122
A61K 45/06

US Classification:

424489, 424 941

Abstract:

The invention provides methods and compositions for treatment of a subject with a solid tumor comprising administration of Coenzyme Q10 (CoQ10), particularly when the subject has failed at least one prior chemotherapeutic regimen.

US Patent:

59911980, Nov 23, 1999

Filed:

Apr 2, 1998

Appl. No.:

9/054423

Inventors:

Paul Jei-Zen Song - Sunnyvale CA
Keyhan Sinai - Santa Clara CA

Assignee:

NexFlash Technologies, Inc. - Santa Clara CA

International Classification:

G11C 1604

US Classification:

36518511

Abstract:

A semiconductor non-volatile memory device is disclosed which is based on the use of Fowler-Nordheim electron tunneling to charge and discharge the isolated gates of the storage cells. Furthermore, the disclosed memory device includes global decoder circuitry capable of passing either positive or negative voltages to a set of global word lines controlling-local decoder circuitry, said local controller circuitry in turn controlling row select lines or local word lines. Each local decoder controls a multiplicity of word lines. The local decoder circuitry is located in physical proximity to specific memory sectors thus resulting in an improved layout of the decoder circuitry and enabling the selection of one of the multiplicity of word lines within said sector by means of electrical control lines. The electrical control lines select one of the multiplicity of rows within a memory sector and deselect all the remaining rows. Logic control circuitry is provided to control the logic of the local row decoders.

US Patent:

60695196, May 30, 2000

Filed:

Jun 10, 1998

Appl. No.:

9/095199

Inventors:

Paul Jei-Zen Song - Sunnyvale CA

Assignee:

Integrated Silicon Solution Inc. - Santa Clara CA

International Classification:

G11C 700

US Classification:

327536

Abstract:

A distribution charge pump is disclosed that reduces leakage from a VPP node where a programming voltage (VPP) is provided. The distribution charge pump includes a pump section and a biasing network. The pump section, in response to input signals at 0V or VCC, generates corresponding output signals at 0V or VPP, respectively. Typically, VCC can be between 2V and 5V and VPP can be between 11V and 15V. The pump section includes two n-channel transistors that bootstrap each other to cooperatively pull up the output node to VPP in response to an input signal of VCC. When the charge pump is active, one of the transistors, a native-mode device, transfers charge from the VPP node to an internal node where charge is stored by a capacitor. The biasing network reduces leakage current from the VPP node through the native-mode transistor when the charge pump is inactive. The biasing network accomplishes this by setting the voltage at the internal node when the charge pump is inactive so that the native-mode transistor is back biased and, therefore, off.

US Patent:

56423101, Jun 24, 1997

Filed:

Feb 2, 1996

Appl. No.:

8/596432

Inventors:

Paul Jei-zen Song - Sunnyvale CA

Assignee:

Integrated Silicon Solution Inc. - Santa Clara CA

International Classification:

G11C 700

US Classification:

36518529

Abstract:

A double erase control circuit is disclosed for use with an EEPROM/flash memory system wherein each memory cell can be read, erased or programmed based, in part, on the voltage level of a word line coupled to the gate of each of the memory cells. A host selectively erases flash memory cells by placing 0 VDC on the word lines and a large positive voltage (10. 4 VDC to 10. 8 VDC) on an array virtual ground supply (VVSS) line while the drains of the memory cells float. The voltage and current on the VVSS line are simultaneously controlled using voltage and current control circuitry that are responsive to a high erase signal that is asserted by the host during an erase operation. When the erase signal is high, the voltage control circuitry uses a comparator, a stable reference voltage (1. 28 VDC) derived from a band-gap reference and a feedback loop to maintain VVSS at the target source erase voltage (i. e. , 10. 4 VDC to 10. 8 VDC).

US Patent:

55684254, Oct 22, 1996

Filed:

Feb 2, 1996

Appl. No.:

8/596408

Inventors:

Paul J. Song - Sunnyvale CA

Assignee:

Integrated Silicon Solution, Inc. - Sunnyvale CA

International Classification:

G11C 1300

US Classification:

36518533

Abstract:

A program drain voltage control system is disclosed for use within an EPROM/flash memory system wherein each memory cell is coupled in series with plural y selection transistors. When the EPROM/flash memory system is in programming mode, the control system maintains the program drain voltage of EPROM/flash memory cells being programmed at a target drain voltage (+6. 1 VDC ). Drain voltage control is accomplished using a current control circuit and a voltage control circuit. The voltage control circuit uses a comparator driven by a voltage reference signal (+1. 28 VDC) derived from the bandgap reference and by a voltage divider output. When the output from the voltage divider is larger than the reference voltage, the comparator output goes high, turning on a pulldown transistor, which pulls down the node where the target voltage is to be established. So that the target drain voltage is correctly mirrored at the drain of the memory cells being programmed, the target drain voltage is coupled to the drain of a first of the y selector transistor through a like number of identical pass transistors. The current control circuit uses a n-channel native transistor whose gate is coupled to the same voltage reference (1.

US Patent:

58187669, Oct 6, 1998

Filed:

Mar 5, 1997

Appl. No.:

8/811946

Inventors:

Paul Jei-Zen Song - Sunnyvale CA

Assignee:

Integrated Silicon Solution Inc. - Santa Clara CA

International Classification:

G11C 700

US Classification:

36518911

Abstract:

A program drain voltage pump is provided that employs multiple pumping sections that are adaptively controlled to provide a pumped drain voltage (VD) that rises smoothly and rapidly to an optimum VD level for programming EPROM or flash memory cells and maintains VD at the optimum level with minimal ripple. The pumping sections are configured to pump a common VD node that is coupled to the drains of the EPROM or flash memory cells. Each pumping section is driven by a clock signal whose pulses are out of phase with the clock signals driving the other pumping sections. All of the clock signals have roughly the same frequency. Due to the staggered clocks, each pump is activated during a different respective time period, which smooths out VD. Additionally, to provide an even faster and smoother pumped VD than with multiphase clocking alone, an embedded controller is provided that adaptively adjusts the frequency and slew rate of the various clock pulses throughout the pumping operation, which alters the amount by which VD is raised for a given clock pulse.

US Patent:

55792626, Nov 26, 1996

Filed:

Feb 5, 1996

Appl. No.:

8/596505

Inventors:

Paul J. Song - Sunnyvale CA

Assignee:

Integrated Silicon Solution, Inc. - Sunnyvale CA

International Classification:

G11C 1300

US Classification:

36518533

Abstract:

A program verify and erase verify control circuit is disclosed for use with an EEPROM/flash memory system wherein each memory cell can be read, erased or programmed based, in part, on the voltage level of a word line coupled to the gate of each of the memory cells. Program operations are verified by placing a worst case (i. e. , highest) read voltage on the word lines of programmed memory cells. Similarly, erase operations are verified by placing a worst case (i. e. , lowest) read voltage on the word lines of erased memory cells. So that there worst case voltages are stable and reproducible, they are generated using a feedback control circuit consisting of a comparator driven by a bandgap voltage reference (+1. 28 VDC ), various feedback transistors and a voltage divider network. The worst case program verification voltage (+6.

US Patent:

60317779, Feb 29, 2000

Filed:

Jun 10, 1998

Appl. No.:

9/095176

Inventors:

Julia S. C. Chan - Saratoga CA
Paul Jei-Zen Song - Sunnyvale CA

Assignee:

Integrated Silicon Solution, Inc. - Santa Clara CA
Nexflash Technologies, Inc. - Santa Clara CA

International Classification:

G11C 702

US Classification:

365210

Abstract:

A high speed memory cell current measurement circuit uses an on-chip reference current circuit that generates a reference current Iref. The reference current circuit includes a first current source transistor. An on-chip current comparison circuit has a second current source transistor that is coupled to the first current source transistor so as to mirror the reference current Iref at a fixed current ratio WR. The current comparison circuit has a current connection path connecting the second current source transistor to a memory cell in the semiconductor memory device whose current is to be compared with Iref/WR. The memory cell is selected from the cells in a memory array using the device's on-chip address decoder circuitry. An on-chip result generation subcircuit, coupled to the current connection path between the second current source transistor and the memory cell, produces a Result signal that indicates whether current flowing through the memory cell is more or less than Iref/WR. In one mode of operation the on-chip reference current circuit is coupled to an on-chip connection pad suitable for connection to an external current source that determines the reference current.